hardware.h 2.6 KB

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  1. /*
  2. * hardware.h
  3. *
  4. * hardware specific header
  5. *
  6. * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  16. * GNU General Public License for more details.
  17. */
  18. #ifndef __AM33XX_HARDWARE_H
  19. #define __AM33XX_HARDWARE_H
  20. #include <asm/arch/omap.h>
  21. #ifdef CONFIG_AM33XX
  22. #include <asm/arch/hardware_am33xx.h>
  23. #elif defined(CONFIG_TI814X)
  24. #include <asm/arch/hardware_ti814x.h>
  25. #endif
  26. /* Module base addresses */
  27. #define UART0_BASE 0x44E09000
  28. /* DM Timer base addresses */
  29. #define DM_TIMER0_BASE 0x4802C000
  30. #define DM_TIMER1_BASE 0x4802E000
  31. #define DM_TIMER2_BASE 0x48040000
  32. #define DM_TIMER3_BASE 0x48042000
  33. #define DM_TIMER4_BASE 0x48044000
  34. #define DM_TIMER5_BASE 0x48046000
  35. #define DM_TIMER6_BASE 0x48048000
  36. #define DM_TIMER7_BASE 0x4804A000
  37. /* GPIO Base address */
  38. #define GPIO0_BASE 0x48032000
  39. #define GPIO1_BASE 0x4804C000
  40. #define GPIO2_BASE 0x481AC000
  41. /* BCH Error Location Module */
  42. #define ELM_BASE 0x48080000
  43. /* Watchdog Timer */
  44. #define WDT_BASE 0x44E35000
  45. /* Control Module Base Address */
  46. #define CTRL_BASE 0x44E10000
  47. #define CTRL_DEVICE_BASE 0x44E10600
  48. /* PRCM Base Address */
  49. #define PRCM_BASE 0x44E00000
  50. /* EMIF Base address */
  51. #define EMIF4_0_CFG_BASE 0x4C000000
  52. #define EMIF4_1_CFG_BASE 0x4D000000
  53. /* PLL related registers */
  54. #define CM_PER 0x44E00000
  55. #define CM_WKUP 0x44E00400
  56. #define CM_DPLL 0x44E00500
  57. #define CM_DEVICE 0x44E00700
  58. #define CM_RTC 0x44E00800
  59. #define CM_CEFUSE 0x44E00A00
  60. #define PRM_DEVICE 0x44E00F00
  61. /* VTP Base address */
  62. #define VTP1_CTRL_ADDR 0x48140E10
  63. /* DDR Base address */
  64. #define DDR_CTRL_ADDR 0x44E10E04
  65. #define DDR_CONTROL_BASE_ADDR 0x44E11404
  66. #define DDR_PHY_CMD_ADDR2 0x47C0C800
  67. #define DDR_PHY_DATA_ADDR2 0x47C0C8C8
  68. /* UART */
  69. #define DEFAULT_UART_BASE UART0_BASE
  70. #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
  71. #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
  72. /* GPMC Base address */
  73. #define GPMC_BASE 0x50000000
  74. /* CPSW Config space */
  75. #define CPSW_BASE 0x4A100000
  76. #define CPSW_MDIO_BASE 0x4A101000
  77. /* RTC base address */
  78. #define RTC_BASE 0x44E3E000
  79. /* OTG */
  80. #define USB0_OTG_BASE 0x47401000
  81. #define USB1_OTG_BASE 0x47401800
  82. #endif /* __AM33XX_HARDWARE_H */