mpc8xxx_spi.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
  4. * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
  5. */
  6. #include <common.h>
  7. #include <malloc.h>
  8. #include <spi.h>
  9. #include <asm/mpc8xxx_spi.h>
  10. #define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
  11. #define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */
  12. #define SPI_MODE_LOOP (0x80000000 >> 1) /* Loopback mode */
  13. #define SPI_MODE_REV (0x80000000 >> 5) /* Reverse mode - MSB first */
  14. #define SPI_MODE_MS (0x80000000 >> 6) /* Always master */
  15. #define SPI_MODE_EN (0x80000000 >> 7) /* Enable interface */
  16. #define SPI_TIMEOUT 1000
  17. struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
  18. unsigned int max_hz, unsigned int mode)
  19. {
  20. struct spi_slave *slave;
  21. if (!spi_cs_is_valid(bus, cs))
  22. return NULL;
  23. slave = spi_alloc_slave_base(bus, cs);
  24. if (!slave)
  25. return NULL;
  26. /*
  27. * TODO: Some of the code in spi_init() should probably move
  28. * here, or into spi_claim_bus() below.
  29. */
  30. return slave;
  31. }
  32. void spi_free_slave(struct spi_slave *slave)
  33. {
  34. free(slave);
  35. }
  36. void spi_init(void)
  37. {
  38. volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
  39. /*
  40. * SPI pins on the MPC83xx are not muxed, so all we do is initialize
  41. * some registers
  42. */
  43. spi->mode = SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN;
  44. spi->mode = (spi->mode & 0xfff0ffff) | BIT(16); /* Use SYSCLK / 8
  45. (16.67MHz typ.) */
  46. spi->event = 0xffffffff; /* Clear all SPI events */
  47. spi->mask = 0x00000000; /* Mask all SPI interrupts */
  48. spi->com = 0; /* LST bit doesn't do anything, so disregard */
  49. }
  50. int spi_claim_bus(struct spi_slave *slave)
  51. {
  52. return 0;
  53. }
  54. void spi_release_bus(struct spi_slave *slave)
  55. {
  56. }
  57. int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
  58. void *din, unsigned long flags)
  59. {
  60. volatile spi8xxx_t *spi = &((immap_t *) (CONFIG_SYS_IMMR))->spi;
  61. unsigned int tmpdout, tmpdin, event;
  62. int numBlks = DIV_ROUND_UP(bitlen, 32);
  63. int tm, isRead = 0;
  64. unsigned char charSize = 32;
  65. debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n",
  66. slave->bus, slave->cs, *(uint *) dout, *(uint *) din, bitlen);
  67. if (flags & SPI_XFER_BEGIN)
  68. spi_cs_activate(slave);
  69. spi->event = 0xffffffff; /* Clear all SPI events */
  70. /* handle data in 32-bit chunks */
  71. while (numBlks--) {
  72. tmpdout = 0;
  73. charSize = (bitlen >= 32 ? 32 : bitlen);
  74. /* Shift data so it's msb-justified */
  75. tmpdout = *(u32 *) dout >> (32 - charSize);
  76. /* The LEN field of the SPMODE register is set as follows:
  77. *
  78. * Bit length setting
  79. * len <= 4 3
  80. * 4 < len <= 16 len - 1
  81. * len > 16 0
  82. */
  83. spi->mode &= ~SPI_MODE_EN;
  84. if (bitlen <= 16) {
  85. if (bitlen <= 4)
  86. spi->mode = (spi->mode & 0xff0fffff) |
  87. (3 << 20);
  88. else
  89. spi->mode = (spi->mode & 0xff0fffff) |
  90. ((bitlen - 1) << 20);
  91. } else {
  92. spi->mode = (spi->mode & 0xff0fffff);
  93. /* Set up the next iteration if sending > 32 bits */
  94. bitlen -= 32;
  95. dout += 4;
  96. }
  97. spi->mode |= SPI_MODE_EN;
  98. spi->tx = tmpdout; /* Write the data out */
  99. debug("*** spi_xfer: ... %08x written\n", tmpdout);
  100. /*
  101. * Wait for SPI transmit to get out
  102. * or time out (1 second = 1000 ms)
  103. * The NE event must be read and cleared first
  104. */
  105. for (tm = 0, isRead = 0; tm < SPI_TIMEOUT; ++tm) {
  106. event = spi->event;
  107. if (event & SPI_EV_NE) {
  108. tmpdin = spi->rx;
  109. spi->event |= SPI_EV_NE;
  110. isRead = 1;
  111. *(u32 *) din = (tmpdin << (32 - charSize));
  112. if (charSize == 32) {
  113. /* Advance output buffer by 32 bits */
  114. din += 4;
  115. }
  116. }
  117. /*
  118. * Only bail when we've had both NE and NF events.
  119. * This will cause timeouts on RO devices, so maybe
  120. * in the future put an arbitrary delay after writing
  121. * the device. Arbitrary delays suck, though...
  122. */
  123. if (isRead && (event & SPI_EV_NF))
  124. break;
  125. }
  126. if (tm >= SPI_TIMEOUT)
  127. puts("*** spi_xfer: Time out during SPI transfer");
  128. debug("*** spi_xfer: transfer ended. Value=%08x\n", tmpdin);
  129. }
  130. if (flags & SPI_XFER_END)
  131. spi_cs_deactivate(slave);
  132. return 0;
  133. }