dwapb_gpio.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Marek Vasut <marex@denx.de>
  4. *
  5. * DesignWare APB GPIO driver
  6. */
  7. #include <common.h>
  8. #include <malloc.h>
  9. #include <asm/arch/gpio.h>
  10. #include <asm/gpio.h>
  11. #include <asm/io.h>
  12. #include <dm.h>
  13. #include <dm/device-internal.h>
  14. #include <dm/lists.h>
  15. #include <dm/root.h>
  16. #include <errno.h>
  17. #include <reset.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define GPIO_SWPORT_DR(p) (0x00 + (p) * 0xc)
  20. #define GPIO_SWPORT_DDR(p) (0x04 + (p) * 0xc)
  21. #define GPIO_INTEN 0x30
  22. #define GPIO_INTMASK 0x34
  23. #define GPIO_INTTYPE_LEVEL 0x38
  24. #define GPIO_INT_POLARITY 0x3c
  25. #define GPIO_INTSTATUS 0x40
  26. #define GPIO_PORTA_DEBOUNCE 0x48
  27. #define GPIO_PORTA_EOI 0x4c
  28. #define GPIO_EXT_PORT(p) (0x50 + (p) * 4)
  29. struct gpio_dwapb_priv {
  30. struct reset_ctl_bulk resets;
  31. };
  32. struct gpio_dwapb_platdata {
  33. const char *name;
  34. int bank;
  35. int pins;
  36. fdt_addr_t base;
  37. };
  38. static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin)
  39. {
  40. struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
  41. clrbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
  42. return 0;
  43. }
  44. static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin,
  45. int val)
  46. {
  47. struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
  48. setbits_le32(plat->base + GPIO_SWPORT_DDR(plat->bank), 1 << pin);
  49. if (val)
  50. setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
  51. else
  52. clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
  53. return 0;
  54. }
  55. static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin)
  56. {
  57. struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
  58. return !!(readl(plat->base + GPIO_EXT_PORT(plat->bank)) & (1 << pin));
  59. }
  60. static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val)
  61. {
  62. struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
  63. if (val)
  64. setbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
  65. else
  66. clrbits_le32(plat->base + GPIO_SWPORT_DR(plat->bank), 1 << pin);
  67. return 0;
  68. }
  69. static int dwapb_gpio_get_function(struct udevice *dev, unsigned offset)
  70. {
  71. struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
  72. u32 gpio;
  73. gpio = readl(plat->base + GPIO_SWPORT_DDR(plat->bank));
  74. if (gpio & BIT(offset))
  75. return GPIOF_OUTPUT;
  76. else
  77. return GPIOF_INPUT;
  78. }
  79. static const struct dm_gpio_ops gpio_dwapb_ops = {
  80. .direction_input = dwapb_gpio_direction_input,
  81. .direction_output = dwapb_gpio_direction_output,
  82. .get_value = dwapb_gpio_get_value,
  83. .set_value = dwapb_gpio_set_value,
  84. .get_function = dwapb_gpio_get_function,
  85. };
  86. static int gpio_dwapb_reset(struct udevice *dev)
  87. {
  88. int ret;
  89. struct gpio_dwapb_priv *priv = dev_get_priv(dev);
  90. ret = reset_get_bulk(dev, &priv->resets);
  91. if (ret) {
  92. /* Return 0 if error due to !CONFIG_DM_RESET and reset
  93. * DT property is not present.
  94. */
  95. if (ret == -ENOENT || ret == -ENOTSUPP)
  96. return 0;
  97. dev_warn(dev, "Can't get reset: %d\n", ret);
  98. return ret;
  99. }
  100. ret = reset_deassert_bulk(&priv->resets);
  101. if (ret) {
  102. reset_release_bulk(&priv->resets);
  103. dev_err(dev, "Failed to reset: %d\n", ret);
  104. return ret;
  105. }
  106. return 0;
  107. }
  108. static int gpio_dwapb_probe(struct udevice *dev)
  109. {
  110. struct gpio_dev_priv *priv = dev_get_uclass_priv(dev);
  111. struct gpio_dwapb_platdata *plat = dev->platdata;
  112. if (!plat) {
  113. /* Reset on parent device only */
  114. return gpio_dwapb_reset(dev);
  115. }
  116. priv->gpio_count = plat->pins;
  117. priv->bank_name = plat->name;
  118. return 0;
  119. }
  120. static int gpio_dwapb_bind(struct udevice *dev)
  121. {
  122. struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
  123. const void *blob = gd->fdt_blob;
  124. struct udevice *subdev;
  125. fdt_addr_t base;
  126. int ret, node, bank = 0;
  127. /* If this is a child device, there is nothing to do here */
  128. if (plat)
  129. return 0;
  130. base = dev_read_addr(dev);
  131. if (base == FDT_ADDR_T_NONE) {
  132. debug("Can't get the GPIO register base address\n");
  133. return -ENXIO;
  134. }
  135. for (node = fdt_first_subnode(blob, dev_of_offset(dev));
  136. node > 0;
  137. node = fdt_next_subnode(blob, node)) {
  138. if (!fdtdec_get_bool(blob, node, "gpio-controller"))
  139. continue;
  140. plat = devm_kcalloc(dev, 1, sizeof(*plat), GFP_KERNEL);
  141. if (!plat)
  142. return -ENOMEM;
  143. plat->base = base;
  144. plat->bank = bank;
  145. plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0);
  146. plat->name = fdt_stringlist_get(blob, node, "bank-name", 0,
  147. NULL);
  148. ret = device_bind(dev, dev->driver, plat->name,
  149. plat, -1, &subdev);
  150. if (ret)
  151. return ret;
  152. dev_set_of_offset(subdev, node);
  153. bank++;
  154. }
  155. return 0;
  156. }
  157. static int gpio_dwapb_remove(struct udevice *dev)
  158. {
  159. struct gpio_dwapb_platdata *plat = dev_get_platdata(dev);
  160. struct gpio_dwapb_priv *priv = dev_get_priv(dev);
  161. if (!plat && priv)
  162. return reset_release_bulk(&priv->resets);
  163. return 0;
  164. }
  165. static const struct udevice_id gpio_dwapb_ids[] = {
  166. { .compatible = "snps,dw-apb-gpio" },
  167. { }
  168. };
  169. U_BOOT_DRIVER(gpio_dwapb) = {
  170. .name = "gpio-dwapb",
  171. .id = UCLASS_GPIO,
  172. .of_match = gpio_dwapb_ids,
  173. .ops = &gpio_dwapb_ops,
  174. .bind = gpio_dwapb_bind,
  175. .probe = gpio_dwapb_probe,
  176. .remove = gpio_dwapb_remove,
  177. .priv_auto_alloc_size = sizeof(struct gpio_dwapb_priv),
  178. };