clock-k2e.h 993 B

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  1. /*
  2. * K2E: Clock management APIs
  3. *
  4. * (C) Copyright 2012-2014
  5. * Texas Instruments Incorporated, <www.ti.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #ifndef __ASM_ARCH_CLOCK_K2E_H
  10. #define __ASM_ARCH_CLOCK_K2E_H
  11. #define PLLSET_CMD_LIST "<pa|ddr3>"
  12. #define KS2_CLK1_6 sys_clk0_6_clk
  13. #define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
  14. #define CORE_PLL_850 {CORE_PLL, 17, 1, 2}
  15. #define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
  16. #define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
  17. #define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
  18. #define CORE_PLL_1250 {CORE_PLL, 25, 1, 2}
  19. #define CORE_PLL_1350 {CORE_PLL, 27, 1, 2}
  20. #define CORE_PLL_1400 {CORE_PLL, 28, 1, 2}
  21. #define CORE_PLL_1500 {CORE_PLL, 30, 1, 2}
  22. #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
  23. #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
  24. #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
  25. #define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
  26. /* k2e DEV supports 800, 850, 1000, 1250, 1350, 1400, 1500 MHz */
  27. #define DEV_SUPPORTED_SPEEDS 0xFFF
  28. #define ARM_SUPPORTED_SPEEDS 0
  29. #endif