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u-boot
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arch
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arm
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include
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asm
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arch-am33xx
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hardware_am33xx.h

hardware_am33xx.h 1.6 KB
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  1. /*
    2. 

  2.  * hardware_am33xx.h
    3. 

  3.  *
    4. 

  4.  * AM33xx hardware specific header
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
    7. 

  7.  *
    8. 

  8.  * SPDX-License-Identifier:	GPL-2.0+
    9. 

  9.  */
    10. 

  10. 

  11. #ifndef __AM33XX_HARDWARE_AM33XX_H
    12. 

  12. #define __AM33XX_HARDWARE_AM33XX_H
    13. 

  13. 

  14. /* Module base addresses */
    15. 

  15. 

  16. /* UART Base Address */
    17. 

  17. #define UART0_BASE			0x44E09000
    18. 

  18. 

  19. /* GPIO Base address */
    20. 

  20. #define GPIO2_BASE			0x481AC000
    21. 

  21. 

  22. /* Watchdog Timer */
    23. 

  23. #define WDT_BASE			0x44E35000
    24. 

  24. 

  25. /* Control Module Base Address */
    26. 

  26. #define CTRL_BASE			0x44E10000
    27. 

  27. #define CTRL_DEVICE_BASE		0x44E10600
    28. 

  28. 

  29. /* PRCM Base Address */
    30. 

  30. #define PRCM_BASE			0x44E00000
    31. 

  31. #define CM_PER				0x44E00000
    32. 

  32. #define CM_WKUP				0x44E00400
    33. 

  33. #define CM_DPLL				0x44E00500
    34. 

  34. #define CM_RTC				0x44E00800
    35. 

  35. 

  36. #define PRM_RSTCTRL			(PRCM_BASE + 0x0F00)
    37. 

  37. #define PRM_RSTST			(PRM_RSTCTRL + 8)
    38. 

  38. 

  39. /* VTP Base address */
    40. 

  40. #define VTP0_CTRL_ADDR			0x44E10E0C
    41. 

  41. #define VTP1_CTRL_ADDR			0x48140E10
    42. 

  42. #define PRM_DEVICE_INST			0x44E00F00
    43. 

  43. 

  44. /* DDR Base address */
    45. 

  45. #define DDR_PHY_CMD_ADDR		0x44E12000
    46. 

  46. #define DDR_PHY_DATA_ADDR		0x44E120C8
    47. 

  47. #define DDR_PHY_CMD_ADDR2		0x47C0C800
    48. 

  48. #define DDR_PHY_DATA_ADDR2		0x47C0C8C8
    49. 

  49. #define DDR_DATA_REGS_NR		2
    50. 

  50. 

  51. #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
    52. 

  52. #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
    53. 

  53. 

  54. /* CPSW Config space */
    55. 

  55. #define CPSW_MDIO_BASE			0x4A101000
    56. 

  56. 

  57. /* RTC base address */
    58. 

  58. #define RTC_BASE			0x44E3E000
    59. 

  59. 

  60. /* OTG */
    61. 

  61. #define USB0_OTG_BASE			0x47401000
    62. 

  62. #define USB1_OTG_BASE			0x47401800
    63. 

  63. 

  64. /* LCD Controller */
    65. 

  65. #define LCD_CNTL_BASE			0x4830E000
    66. 

  66. 

  67. /* PWMSS */
    68. 

  68. #define PWMSS0_BASE			0x48300000
    69. 

  69. #define AM33XX_ECAP0_BASE		0x48300100
    70. 

  70. #define AM33XX_EPWM_BASE		0x48300200
    71. 

  71. 

  72. #endif /* __AM33XX_HARDWARE_AM33XX_H */
    73.