power.c 3.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142
  1. /*
  2. * Copyright (C) 2012 Samsung Electronics
  3. * Donghwa Lee <dh09.lee@samsung.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/io.h>
  25. #include <asm/arch/power.h>
  26. static void exynos4_mipi_phy_control(unsigned int dev_index,
  27. unsigned int enable)
  28. {
  29. struct exynos4_power *pmu =
  30. (struct exynos4_power *)samsung_get_base_power();
  31. unsigned int addr, cfg = 0;
  32. if (dev_index == 0)
  33. addr = (unsigned int)&pmu->mipi_phy0_control;
  34. else
  35. addr = (unsigned int)&pmu->mipi_phy1_control;
  36. cfg = readl(addr);
  37. if (enable)
  38. cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
  39. else
  40. cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
  41. writel(cfg, addr);
  42. }
  43. void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
  44. {
  45. if (cpu_is_exynos4())
  46. exynos4_mipi_phy_control(dev_index, enable);
  47. }
  48. void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
  49. {
  50. struct exynos5_power *power =
  51. (struct exynos5_power *)samsung_get_base_power();
  52. if (enable) {
  53. /* Enabling USBHOST_PHY */
  54. setbits_le32(&power->usbhost_phy_control,
  55. POWER_USB_HOST_PHY_CTRL_EN);
  56. } else {
  57. /* Disabling USBHOST_PHY */
  58. clrbits_le32(&power->usbhost_phy_control,
  59. POWER_USB_HOST_PHY_CTRL_EN);
  60. }
  61. }
  62. void set_usbhost_phy_ctrl(unsigned int enable)
  63. {
  64. if (cpu_is_exynos5())
  65. exynos5_set_usbhost_phy_ctrl(enable);
  66. }
  67. static void exynos5_dp_phy_control(unsigned int enable)
  68. {
  69. unsigned int cfg;
  70. struct exynos5_power *power =
  71. (struct exynos5_power *)samsung_get_base_power();
  72. cfg = readl(&power->dptx_phy_control);
  73. if (enable)
  74. cfg |= EXYNOS_DP_PHY_ENABLE;
  75. else
  76. cfg &= ~EXYNOS_DP_PHY_ENABLE;
  77. writel(cfg, &power->dptx_phy_control);
  78. }
  79. void set_dp_phy_ctrl(unsigned int enable)
  80. {
  81. if (cpu_is_exynos5())
  82. exynos5_dp_phy_control(enable);
  83. }
  84. static void exynos5_set_ps_hold_ctrl(void)
  85. {
  86. struct exynos5_power *power =
  87. (struct exynos5_power *)samsung_get_base_power();
  88. /* Set PS-Hold high */
  89. setbits_le32(&power->ps_hold_control,
  90. EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
  91. }
  92. void set_ps_hold_ctrl(void)
  93. {
  94. if (cpu_is_exynos5())
  95. exynos5_set_ps_hold_ctrl();
  96. }
  97. static void exynos5_set_xclkout(void)
  98. {
  99. struct exynos5_power *power =
  100. (struct exynos5_power *)samsung_get_base_power();
  101. /* use xxti for xclk out */
  102. clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
  103. PMU_DEBUG_XXTI);
  104. }
  105. void set_xclkout(void)
  106. {
  107. if (cpu_is_exynos5())
  108. exynos5_set_xclkout();
  109. }
  110. /* Enables hardware tripping to power off the system when TMU fails */
  111. void set_hw_thermal_trip(void)
  112. {
  113. if (cpu_is_exynos5()) {
  114. struct exynos5_power *power =
  115. (struct exynos5_power *)samsung_get_base_power();
  116. /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
  117. setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
  118. }
  119. }