mrc_util.h 4.3 KB

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  1. /*
  2. * Copyright (C) 2013, Intel Corporation
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. *
  5. * Ported from Intel released Quark UEFI BIOS
  6. * QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei
  7. *
  8. * SPDX-License-Identifier: Intel
  9. */
  10. #ifndef _MRC_UTIL_H_
  11. #define _MRC_UTIL_H_
  12. /* Turn on this macro to enable MRC debugging output */
  13. #undef MRC_DEBUG
  14. /* MRC Debug Support */
  15. #define DPF debug_cond
  16. /* debug print type */
  17. #ifdef MRC_DEBUG
  18. #define D_ERROR 0x0001
  19. #define D_INFO 0x0002
  20. #define D_REGRD 0x0004
  21. #define D_REGWR 0x0008
  22. #define D_FCALL 0x0010
  23. #define D_TRN 0x0020
  24. #define D_TIME 0x0040
  25. #else
  26. #define D_ERROR 0
  27. #define D_INFO 0
  28. #define D_REGRD 0
  29. #define D_REGWR 0
  30. #define D_FCALL 0
  31. #define D_TRN 0
  32. #define D_TIME 0
  33. #endif
  34. #define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__)
  35. #define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__)
  36. #define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__)
  37. /* Generic Register Bits */
  38. #define BIT0 0x00000001
  39. #define BIT1 0x00000002
  40. #define BIT2 0x00000004
  41. #define BIT3 0x00000008
  42. #define BIT4 0x00000010
  43. #define BIT5 0x00000020
  44. #define BIT6 0x00000040
  45. #define BIT7 0x00000080
  46. #define BIT8 0x00000100
  47. #define BIT9 0x00000200
  48. #define BIT10 0x00000400
  49. #define BIT11 0x00000800
  50. #define BIT12 0x00001000
  51. #define BIT13 0x00002000
  52. #define BIT14 0x00004000
  53. #define BIT15 0x00008000
  54. #define BIT16 0x00010000
  55. #define BIT17 0x00020000
  56. #define BIT18 0x00040000
  57. #define BIT19 0x00080000
  58. #define BIT20 0x00100000
  59. #define BIT21 0x00200000
  60. #define BIT22 0x00400000
  61. #define BIT23 0x00800000
  62. #define BIT24 0x01000000
  63. #define BIT25 0x02000000
  64. #define BIT26 0x04000000
  65. #define BIT27 0x08000000
  66. #define BIT28 0x10000000
  67. #define BIT29 0x20000000
  68. #define BIT30 0x40000000
  69. #define BIT31 0x80000000
  70. /* Message Bus Port */
  71. #define MEM_CTLR 0x01
  72. #define HOST_BRIDGE 0x03
  73. #define MEM_MGR 0x05
  74. #define HTE 0x11
  75. #define DDRPHY 0x12
  76. /* number of sample points */
  77. #define SAMPLE_CNT 3
  78. /* number of PIs to increment per sample */
  79. #define SAMPLE_DLY 26
  80. enum {
  81. /* indicates to decrease delays when looking for edge */
  82. BACKWARD,
  83. /* indicates to increase delays when looking for edge */
  84. FORWARD
  85. };
  86. enum {
  87. RCVN,
  88. WDQS,
  89. WDQX,
  90. RDQS,
  91. VREF,
  92. WCMD,
  93. WCTL,
  94. WCLK,
  95. MAX_ALGOS,
  96. };
  97. void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
  98. void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask);
  99. void mrc_post_code(uint8_t major, uint8_t minor);
  100. void delay_n(uint32_t ns);
  101. void delay_u(uint32_t ms);
  102. void select_mem_mgr(void);
  103. void select_hte(void);
  104. void dram_init_command(uint32_t data);
  105. void dram_wake_command(void);
  106. void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane);
  107. void set_rcvn(uint8_t channel, uint8_t rank,
  108. uint8_t byte_lane, uint32_t pi_count);
  109. uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane);
  110. void set_rdqs(uint8_t channel, uint8_t rank,
  111. uint8_t byte_lane, uint32_t pi_count);
  112. uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
  113. void set_wdqs(uint8_t channel, uint8_t rank,
  114. uint8_t byte_lane, uint32_t pi_count);
  115. uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane);
  116. void set_wdq(uint8_t channel, uint8_t rank,
  117. uint8_t byte_lane, uint32_t pi_count);
  118. uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane);
  119. void set_wcmd(uint8_t channel, uint32_t pi_count);
  120. uint32_t get_wcmd(uint8_t channel);
  121. void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
  122. uint32_t get_wclk(uint8_t channel, uint8_t rank);
  123. void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count);
  124. uint32_t get_wctl(uint8_t channel, uint8_t rank);
  125. void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting);
  126. uint32_t get_vref(uint8_t channel, uint8_t byte_lane);
  127. uint32_t get_addr(uint8_t channel, uint8_t rank);
  128. uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel,
  129. uint8_t rank, bool rcvn);
  130. void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[],
  131. uint8_t channel, uint8_t rank, bool rcvn);
  132. uint32_t byte_lane_mask(struct mrc_params *mrc_params);
  133. uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address);
  134. uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address);
  135. void lfsr32(uint32_t *lfsr_ptr);
  136. void clear_pointers(void);
  137. void print_timings(struct mrc_params *mrc_params);
  138. #endif /* _MRC_UTIL_H_ */