ddr3_training_ip.h 4.5 KB

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  1. /*
  2. * Copyright (C) Marvell International Ltd. and its affiliates
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #ifndef _DDR3_TRAINING_IP_H_
  7. #define _DDR3_TRAINING_IP_H_
  8. #include "ddr3_training_ip_def.h"
  9. #include "ddr_topology_def.h"
  10. #include "ddr_training_ip_db.h"
  11. #define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.29."
  12. #define MAX_CS_NUM 4
  13. #define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM)
  14. #define MAX_DQ_NUM 40
  15. #define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
  16. #define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
  17. #define INIT_CONTROLLER_MASK_BIT 0x00000001
  18. #define STATIC_LEVELING_MASK_BIT 0x00000002
  19. #define SET_LOW_FREQ_MASK_BIT 0x00000004
  20. #define LOAD_PATTERN_MASK_BIT 0x00000008
  21. #define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
  22. #define WRITE_LEVELING_MASK_BIT 0x00000020
  23. #define LOAD_PATTERN_2_MASK_BIT 0x00000040
  24. #define READ_LEVELING_MASK_BIT 0x00000080
  25. #define SW_READ_LEVELING_MASK_BIT 0x00000100
  26. #define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200
  27. #define PBS_RX_MASK_BIT 0x00000400
  28. #define PBS_TX_MASK_BIT 0x00000800
  29. #define SET_TARGET_FREQ_MASK_BIT 0x00001000
  30. #define ADJUST_DQS_MASK_BIT 0x00002000
  31. #define WRITE_LEVELING_TF_MASK_BIT 0x00004000
  32. #define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000
  33. #define READ_LEVELING_TF_MASK_BIT 0x00010000
  34. #define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
  35. #define DM_PBS_TX_MASK_BIT 0x00040000
  36. #define CENTRALIZATION_RX_MASK_BIT 0x00100000
  37. #define CENTRALIZATION_TX_MASK_BIT 0x00200000
  38. #define TX_EMPHASIS_MASK_BIT 0x00400000
  39. #define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
  40. #define VREF_CALIBRATION_MASK_BIT 0x01000000
  41. enum hws_result {
  42. TEST_FAILED = 0,
  43. TEST_SUCCESS = 1,
  44. NO_TEST_DONE = 2
  45. };
  46. enum hws_training_result {
  47. RESULT_PER_BIT,
  48. RESULT_PER_BYTE
  49. };
  50. enum auto_tune_stage {
  51. INIT_CONTROLLER,
  52. STATIC_LEVELING,
  53. SET_LOW_FREQ,
  54. LOAD_PATTERN,
  55. SET_MEDIUM_FREQ,
  56. WRITE_LEVELING,
  57. LOAD_PATTERN_2,
  58. READ_LEVELING,
  59. WRITE_LEVELING_SUPP,
  60. PBS_RX,
  61. PBS_TX,
  62. SET_TARGET_FREQ,
  63. ADJUST_DQS,
  64. WRITE_LEVELING_TF,
  65. READ_LEVELING_TF,
  66. WRITE_LEVELING_SUPP_TF,
  67. DM_PBS_TX,
  68. VREF_CALIBRATION,
  69. CENTRALIZATION_RX,
  70. CENTRALIZATION_TX,
  71. TX_EMPHASIS,
  72. LOAD_PATTERN_HIGH,
  73. PER_BIT_READ_LEVELING_TF,
  74. MAX_STAGE_LIMIT
  75. };
  76. enum hws_access_type {
  77. ACCESS_TYPE_UNICAST = 0,
  78. ACCESS_TYPE_MULTICAST = 1
  79. };
  80. enum hws_algo_type {
  81. ALGO_TYPE_DYNAMIC,
  82. ALGO_TYPE_STATIC
  83. };
  84. struct init_cntr_param {
  85. int is_ctrl64_bit;
  86. int do_mrs_phy;
  87. int init_phy;
  88. int msys_init;
  89. };
  90. struct pattern_info {
  91. u8 num_of_phases_tx;
  92. u8 tx_burst_size;
  93. u8 delay_between_bursts;
  94. u8 num_of_phases_rx;
  95. u32 start_addr;
  96. u8 pattern_len;
  97. };
  98. /* CL value for each frequency */
  99. struct cl_val_per_freq {
  100. u8 cl_val[DDR_FREQ_LIMIT];
  101. };
  102. struct cs_element {
  103. u8 cs_num;
  104. u8 num_of_cs;
  105. };
  106. struct mode_info {
  107. /* 32 bits representing MRS bits */
  108. u32 reg_mr0[MAX_INTERFACE_NUM];
  109. u32 reg_mr1[MAX_INTERFACE_NUM];
  110. u32 reg_mr2[MAX_INTERFACE_NUM];
  111. u32 reg_m_r3[MAX_INTERFACE_NUM];
  112. /*
  113. * Each element in array represent read_data_sample register delay for
  114. * a specific interface.
  115. * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR
  116. * cycles from read command until data is ready to be fetched from
  117. * the PHY, when accessing CS.
  118. */
  119. u32 read_data_sample[MAX_INTERFACE_NUM];
  120. /*
  121. * Each element in array represent read_data_sample register delay for
  122. * a specific interface.
  123. * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay
  124. * from read command until opening the read mask, when accessing CS.
  125. * This field defines the delay in DDR cycles granularity.
  126. */
  127. u32 read_data_ready[MAX_INTERFACE_NUM];
  128. };
  129. struct hws_tip_freq_config_info {
  130. u8 is_supported;
  131. u8 bw_per_freq;
  132. u8 rate_per_freq;
  133. };
  134. struct hws_cs_config_info {
  135. u32 cs_reg_value;
  136. u32 cs_cbe_value;
  137. };
  138. struct dfx_access {
  139. u8 pipe;
  140. u8 client;
  141. };
  142. struct hws_xsb_info {
  143. struct dfx_access *dfx_table;
  144. };
  145. int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
  146. int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
  147. int hws_ddr3_tip_init_controller(u32 dev_num,
  148. struct init_cntr_param *init_cntr_prm);
  149. int hws_ddr3_tip_load_topology_map(u32 dev_num,
  150. struct hws_topology_map *topology);
  151. int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
  152. int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
  153. int hws_ddr3_tip_read_training_result(u32 dev_num,
  154. enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
  155. int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
  156. u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
  157. u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
  158. #endif /* _DDR3_TRAINING_IP_H_ */