atheros.c 2.3 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495
  1. /*
  2. * Atheros PHY drivers
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. * Copyright 2011, 2013 Freescale Semiconductor, Inc.
  7. * author Andy Fleming
  8. */
  9. #include <phy.h>
  10. static int ar8021_config(struct phy_device *phydev)
  11. {
  12. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  13. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  14. phydev->supported = phydev->drv->features;
  15. return 0;
  16. }
  17. static int ar8035_config(struct phy_device *phydev)
  18. {
  19. int regval;
  20. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
  21. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  22. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  23. regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  24. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
  25. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  26. regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  27. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
  28. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  29. (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
  30. /* select debug reg 5 */
  31. phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5);
  32. /* enable tx delay */
  33. phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100);
  34. }
  35. if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  36. (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) {
  37. /* select debug reg 0 */
  38. phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0);
  39. /* enable rx delay */
  40. phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000);
  41. }
  42. phydev->supported = phydev->drv->features;
  43. genphy_config_aneg(phydev);
  44. genphy_restart_aneg(phydev);
  45. return 0;
  46. }
  47. static struct phy_driver AR8021_driver = {
  48. .name = "AR8021",
  49. .uid = 0x4dd040,
  50. .mask = 0x4ffff0,
  51. .features = PHY_GBIT_FEATURES,
  52. .config = ar8021_config,
  53. .startup = genphy_startup,
  54. .shutdown = genphy_shutdown,
  55. };
  56. static struct phy_driver AR8031_driver = {
  57. .name = "AR8031/AR8033",
  58. .uid = 0x4dd074,
  59. .mask = 0xffffffef,
  60. .features = PHY_GBIT_FEATURES,
  61. .config = ar8035_config,
  62. .startup = genphy_startup,
  63. .shutdown = genphy_shutdown,
  64. };
  65. static struct phy_driver AR8035_driver = {
  66. .name = "AR8035",
  67. .uid = 0x4dd072,
  68. .mask = 0xffffffef,
  69. .features = PHY_GBIT_FEATURES,
  70. .config = ar8035_config,
  71. .startup = genphy_startup,
  72. .shutdown = genphy_shutdown,
  73. };
  74. int phy_atheros_init(void)
  75. {
  76. phy_register(&AR8021_driver);
  77. phy_register(&AR8031_driver);
  78. phy_register(&AR8035_driver);
  79. return 0;
  80. }