cpu_init.c 2.8 KB

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  1. /*
  2. * (C) Copyright 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /*
  7. * File: cpu_init.c
  8. *
  9. * Discription: Contains initialisation functions to setup
  10. * the cpu properly
  11. *
  12. */
  13. #include <common.h>
  14. #include <mpc5xx.h>
  15. #include <watchdog.h>
  16. /*
  17. * Setup essential cpu registers to run
  18. */
  19. void cpu_init_f (volatile immap_t * immr)
  20. {
  21. volatile memctl5xx_t *memctl = &immr->im_memctl;
  22. ulong reg;
  23. /* SYPCR - contains watchdog control. This will enable watchdog */
  24. /* if CONFIG_WATCHDOG is set */
  25. immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
  26. #if defined(CONFIG_WATCHDOG)
  27. reset_5xx_watchdog (immr);
  28. #endif
  29. /* SIUMCR - contains debug pin configuration */
  30. immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
  31. /* Initialize timebase. Unlock TBSCRK */
  32. immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
  33. immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
  34. /* Full IMB bus speed */
  35. immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR;
  36. /* Time base and decrementer will be enables (TBE) */
  37. /* in timer_init() in time.c called from board_init_f(). */
  38. /* Initialize the PIT. Unlock PISCRK */
  39. immr->im_sitk.sitk_piscrk = KAPWR_KEY;
  40. immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
  41. #if !defined(CONFIG_PATI)
  42. /* PATI sest PLL in start.S */
  43. /* PLL (CPU clock) settings */
  44. immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
  45. /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
  46. * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
  47. * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the currentMF
  48. * field value.
  49. */
  50. #if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
  51. reg = CONFIG_SYS_PLPRCR; /* reset control bits */
  52. #else
  53. reg = immr->im_clkrst.car_plprcr;
  54. reg &= PLPRCR_MF_MSK; /* isolate MF field */
  55. reg |= CONFIG_SYS_PLPRCR; /* reset control bits */
  56. #endif
  57. immr->im_clkrst.car_plprcr = reg;
  58. #endif /* !defined(CONFIG_PATI) */
  59. /* System integration timers. CONFIG_SYS_MASK has EBDF configuration */
  60. immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
  61. reg = immr->im_clkrst.car_sccr;
  62. reg &= SCCR_MASK;
  63. reg |= CONFIG_SYS_SCCR;
  64. immr->im_clkrst.car_sccr = reg;
  65. /* Memory Controller */
  66. memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
  67. memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
  68. #if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
  69. memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
  70. memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
  71. #endif
  72. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  73. memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
  74. memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
  75. #endif
  76. #if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
  77. memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
  78. memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
  79. #endif
  80. }
  81. /*
  82. * Initialize higher level parts of cpu
  83. */
  84. int cpu_init_r (void)
  85. {
  86. /* Nothing to do at the moment */
  87. return (0);
  88. }