ap_sh4a_4a.c 3.5 KB

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  1. /*
  2. * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  3. * Copyright (C) 2012 Renesas Solutions Corp.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/processor.h>
  10. #include <netdev.h>
  11. #include <i2c.h>
  12. #define MODEMR (0xFFCC0020)
  13. #define MODEMR_MASK (0x6)
  14. #define MODEMR_533MHZ (0x2)
  15. int checkboard(void)
  16. {
  17. u32 r = readl(MODEMR);
  18. if ((r & MODEMR_MASK) & MODEMR_533MHZ)
  19. puts("CPU Clock: 533MHz\n");
  20. else
  21. puts("CPU Clock: 400MHz\n");
  22. puts("BOARD: Alpha Project. AP-SH4A-4A\n");
  23. return 0;
  24. }
  25. #define MSTPSR1 (0xFFC80044)
  26. #define MSTPCR1 (0xFFC80034)
  27. #define MSTPSR1_GETHER (1 << 14)
  28. /* IPSR3 */
  29. #define ET0_ETXD0 (0x4 << 3)
  30. #define ET0_GTX_CLK_A (0x4 << 6)
  31. #define ET0_ETXD1_A (0x4 << 9)
  32. #define ET0_ETXD2_A (0x4 << 12)
  33. #define ET0_ETXD3_A (0x4 << 15)
  34. #define ET0_ETXD4 (0x3 << 18)
  35. #define ET0_ETXD5_A (0x5 << 21)
  36. #define ET0_ETXD6_A (0x5 << 24)
  37. #define ET0_ETXD7 (0x4 << 27)
  38. #define IPSR3_ETH_ENABLE \
  39. (ET0_ETXD0 | ET0_GTX_CLK_A | ET0_ETXD1_A | ET0_ETXD2_A | \
  40. ET0_ETXD3_A | ET0_ETXD4 | ET0_ETXD5_A | ET0_ETXD6_A | ET0_ETXD7)
  41. /* IPSR4 */
  42. #define ET0_ERXD7 (0x4)
  43. #define ET0_RX_DV (0x4 << 3)
  44. #define ET0_RX_ER (0x4 << 6)
  45. #define ET0_CRS (0x4 << 9)
  46. #define ET0_COL (0x4 << 12)
  47. #define ET0_MDC (0x4 << 15)
  48. #define ET0_MDIO_A (0x3 << 18)
  49. #define ET0_LINK_A (0x3 << 20)
  50. #define ET0_PHY_INT_A (0x3 << 24)
  51. #define IPSR4_ETH_ENABLE \
  52. (ET0_ERXD7 | ET0_RX_DV | ET0_RX_ER | ET0_CRS | ET0_COL | \
  53. ET0_MDC | ET0_MDIO_A | ET0_LINK_A | ET0_PHY_INT_A)
  54. /* IPSR8 */
  55. #define ET0_ERXD0 (0x4 << 20)
  56. #define ET0_ERXD1 (0x4 << 23)
  57. #define ET0_ERXD2_A (0x3 << 26)
  58. #define ET0_ERXD3_A (0x3 << 28)
  59. #define IPSR8_ETH_ENABLE \
  60. (ET0_ERXD0 | ET0_ERXD1 | ET0_ERXD2_A | ET0_ERXD3_A)
  61. /* IPSR10 */
  62. #define RX4_D (0x1 << 22)
  63. #define TX4_D (0x1 << 23)
  64. #define IPSR10_SCIF_ENABLE (RX4_D | TX4_D)
  65. /* IPSR11 */
  66. #define ET0_ERXD4 (0x4 << 4)
  67. #define ET0_ERXD5 (0x4 << 7)
  68. #define ET0_ERXD6 (0x3 << 10)
  69. #define ET0_TX_EN (0x2 << 19)
  70. #define ET0_TX_ER (0x2 << 21)
  71. #define ET0_TX_CLK_A (0x4 << 23)
  72. #define ET0_RX_CLK_A (0x3 << 26)
  73. #define IPSR11_ETH_ENABLE \
  74. (ET0_ERXD4 | ET0_ERXD5 | ET0_ERXD6 | ET0_TX_EN | ET0_TX_ER | \
  75. ET0_TX_CLK_A | ET0_RX_CLK_A)
  76. #define GPSR1_INIT (0xFFFF7FFF)
  77. #define GPSR2_INIT (0x4005FEFF)
  78. #define GPSR3_INIT (0x2EFFFFFF)
  79. #define GPSR4_INIT (0xC7000000)
  80. int board_init(void)
  81. {
  82. u32 data;
  83. /* Set IPSR register */
  84. data = readl(IPSR3);
  85. data |= IPSR3_ETH_ENABLE;
  86. writel(~data, PMMR);
  87. writel(data, IPSR3);
  88. data = readl(IPSR4);
  89. data |= IPSR4_ETH_ENABLE;
  90. writel(~data, PMMR);
  91. writel(data, IPSR4);
  92. data = readl(IPSR8);
  93. data |= IPSR8_ETH_ENABLE;
  94. writel(~data, PMMR);
  95. writel(data, IPSR8);
  96. data = readl(IPSR10);
  97. data |= IPSR10_SCIF_ENABLE;
  98. writel(~data, PMMR);
  99. writel(data, IPSR10);
  100. data = readl(IPSR11);
  101. data |= IPSR11_ETH_ENABLE;
  102. writel(~data, PMMR);
  103. writel(data, IPSR11);
  104. /* GPIO select */
  105. data = GPSR1_INIT;
  106. writel(~data, PMMR);
  107. writel(data, GPSR1);
  108. data = GPSR2_INIT;
  109. writel(~data, PMMR);
  110. writel(data, GPSR2);
  111. data = GPSR3_INIT;
  112. writel(~data, PMMR);
  113. writel(data, GPSR3);
  114. data = GPSR4_INIT;
  115. writel(~data, PMMR);
  116. writel(data, GPSR4);
  117. data = 0x0;
  118. writel(~data, PMMR);
  119. writel(data, GPSR5);
  120. /* mode select */
  121. data = MODESEL2_INIT;
  122. writel(~data, PMMR);
  123. writel(data, MODESEL2);
  124. #if defined(CONFIG_SH_ETHER)
  125. u32 r = readl(MSTPSR1);
  126. if (r & MSTPSR1_GETHER)
  127. writel((r & ~MSTPSR1_GETHER), MSTPCR1);
  128. #endif
  129. return 0;
  130. }
  131. int board_late_init(void)
  132. {
  133. printf("Cannot use I2C to get MAC address\n");
  134. return 0;
  135. }