ds1374.c 6.9 KB

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  1. /*
  2. * (C) Copyright 2001, 2002, 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. * Keith Outwater, keith_outwater@mvis.com`
  5. * Steven Scholz, steven.scholz@imc-berlin.de
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
  27. * DS1374 Real Time Clock (RTC).
  28. *
  29. * based on ds1337.c
  30. */
  31. #include <common.h>
  32. #include <command.h>
  33. #include <rtc.h>
  34. #include <i2c.h>
  35. #if defined(CONFIG_CMD_DATE)
  36. /*---------------------------------------------------------------------*/
  37. #undef DEBUG_RTC
  38. #define DEBUG_RTC
  39. #ifdef DEBUG_RTC
  40. #define DEBUGR(fmt,args...) printf(fmt ,##args)
  41. #else
  42. #define DEBUGR(fmt,args...)
  43. #endif
  44. /*---------------------------------------------------------------------*/
  45. #ifndef CONFIG_SYS_I2C_RTC_ADDR
  46. # define CONFIG_SYS_I2C_RTC_ADDR 0x68
  47. #endif
  48. #if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
  49. # error The DS1374 is specified up to 400kHz in fast mode!
  50. #endif
  51. /*
  52. * RTC register addresses
  53. */
  54. #define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
  55. #define RTC_TOD_CNT_BYTE1_ADDR 0x01
  56. #define RTC_TOD_CNT_BYTE2_ADDR 0x02
  57. #define RTC_TOD_CNT_BYTE3_ADDR 0x03
  58. #define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
  59. #define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
  60. #define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
  61. #define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
  62. #define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
  63. #define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
  64. #define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
  65. #define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
  66. #define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
  67. #define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
  68. #define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
  69. #define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
  70. #define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
  71. #define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
  72. #define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
  73. #define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
  74. const char RtcTodAddr[] = {
  75. RTC_TOD_CNT_BYTE0_ADDR,
  76. RTC_TOD_CNT_BYTE1_ADDR,
  77. RTC_TOD_CNT_BYTE2_ADDR,
  78. RTC_TOD_CNT_BYTE3_ADDR
  79. };
  80. static uchar rtc_read (uchar reg);
  81. static void rtc_write(uchar reg, uchar val, bool set);
  82. static void rtc_write_raw (uchar reg, uchar val);
  83. /*
  84. * Get the current time from the RTC
  85. */
  86. int rtc_get (struct rtc_time *tm){
  87. int rel = 0;
  88. unsigned long time1, time2;
  89. unsigned int limit;
  90. unsigned char tmp;
  91. unsigned int i;
  92. /*
  93. * Since the reads are being performed one byte at a time,
  94. * there is a chance that a carry will occur during the read.
  95. * To detect this, 2 reads are performed and compared.
  96. */
  97. limit = 10;
  98. do {
  99. i = 4;
  100. time1 = 0;
  101. while (i--) {
  102. tmp = rtc_read(RtcTodAddr[i]);
  103. time1 = (time1 << 8) | (tmp & 0xff);
  104. }
  105. i = 4;
  106. time2 = 0;
  107. while (i--) {
  108. tmp = rtc_read(RtcTodAddr[i]);
  109. time2 = (time2 << 8) | (tmp & 0xff);
  110. }
  111. } while ((time1 != time2) && limit--);
  112. if (time1 != time2) {
  113. printf("can't get consistent time from rtc chip\n");
  114. rel = -1;
  115. }
  116. DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1);
  117. to_tm(time1, tm); /* To Gregorian Date */
  118. if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) {
  119. printf ("### Warning: RTC oscillator has stopped\n");
  120. rel = -1;
  121. }
  122. DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  123. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
  124. tm->tm_hour, tm->tm_min, tm->tm_sec);
  125. return rel;
  126. }
  127. /*
  128. * Set the RTC
  129. */
  130. int rtc_set (struct rtc_time *tmp){
  131. unsigned long time;
  132. unsigned i;
  133. DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  134. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  135. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  136. if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
  137. printf("WARNING: year should be between 1970 and 2069!\n");
  138. time = mktime(tmp->tm_year, tmp->tm_mon,
  139. tmp->tm_mday, tmp->tm_hour,
  140. tmp->tm_min, tmp->tm_sec);
  141. DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time);
  142. /* write to RTC_TOD_CNT_BYTEn_ADDR */
  143. for (i = 0; i <= 3; i++) {
  144. rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
  145. time = time >> 8;
  146. }
  147. /* Start clock */
  148. rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false);
  149. return 0;
  150. }
  151. /*
  152. * Reset the RTC. We setting the date back to 1970-01-01.
  153. * We also enable the oscillator output on the SQW/OUT pin and program
  154. * it for 32,768 Hz output. Note that according to the datasheet, turning
  155. * on the square wave output increases the current drain on the backup
  156. * battery to something between 480nA and 800nA.
  157. */
  158. void rtc_reset (void){
  159. struct rtc_time tmp;
  160. /* clear status flags */
  161. rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */
  162. /* Initialise DS1374 oriented to MPC8349E-ADS */
  163. rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
  164. |RTC_CTL_BIT_WACE
  165. |RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE
  166. - set to 0 */
  167. rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
  168. |RTC_CTL_BIT_WDSTR
  169. |RTC_CTL_BIT_RS1
  170. |RTC_CTL_BIT_RS2
  171. |RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin,
  172. set BBSQW and SQW to 32k
  173. - set to 1 */
  174. tmp.tm_year = 1970;
  175. tmp.tm_mon = 1;
  176. tmp.tm_mday= 1;
  177. tmp.tm_hour = 0;
  178. tmp.tm_min = 0;
  179. tmp.tm_sec = 0;
  180. rtc_set(&tmp);
  181. printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
  182. tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
  183. tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
  184. rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true);
  185. rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true);
  186. rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true);
  187. }
  188. /*
  189. * Helper functions
  190. */
  191. static uchar rtc_read (uchar reg)
  192. {
  193. return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
  194. }
  195. static void rtc_write(uchar reg, uchar val, bool set)
  196. {
  197. if (set == true) {
  198. val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
  199. i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
  200. } else {
  201. val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
  202. i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
  203. }
  204. }
  205. static void rtc_write_raw (uchar reg, uchar val)
  206. {
  207. i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
  208. }
  209. #endif