cache-cp15.c 6.5 KB

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  1. /*
  2. * (C) Copyright 2002
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/system.h>
  9. #include <asm/cache.h>
  10. #include <linux/compiler.h>
  11. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  12. DECLARE_GLOBAL_DATA_PTR;
  13. __weak void arm_init_before_mmu(void)
  14. {
  15. }
  16. __weak void arm_init_domains(void)
  17. {
  18. }
  19. static void cp_delay (void)
  20. {
  21. volatile int i;
  22. /* copro seems to need some delay between reading and writing */
  23. for (i = 0; i < 100; i++)
  24. nop();
  25. asm volatile("" : : : "memory");
  26. }
  27. void set_section_dcache(int section, enum dcache_option option)
  28. {
  29. #ifdef CONFIG_ARMV7_LPAE
  30. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  31. /* Need to set the access flag to not fault */
  32. u64 value = TTB_SECT_AP | TTB_SECT_AF;
  33. #else
  34. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  35. u32 value = TTB_SECT_AP;
  36. #endif
  37. /* Add the page offset */
  38. value |= ((u32)section << MMU_SECTION_SHIFT);
  39. /* Add caching bits */
  40. value |= option;
  41. /* Set PTE */
  42. page_table[section] = value;
  43. }
  44. __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
  45. {
  46. debug("%s: Warning: not implemented\n", __func__);
  47. }
  48. void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
  49. enum dcache_option option)
  50. {
  51. #ifdef CONFIG_ARMV7_LPAE
  52. u64 *page_table = (u64 *)gd->arch.tlb_addr;
  53. #else
  54. u32 *page_table = (u32 *)gd->arch.tlb_addr;
  55. #endif
  56. unsigned long startpt, stoppt;
  57. unsigned long upto, end;
  58. end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
  59. start = start >> MMU_SECTION_SHIFT;
  60. debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
  61. option);
  62. for (upto = start; upto < end; upto++)
  63. set_section_dcache(upto, option);
  64. /*
  65. * Make sure range is cache line aligned
  66. * Only CPU maintains page tables, hence it is safe to always
  67. * flush complete cache lines...
  68. */
  69. startpt = (unsigned long)&page_table[start];
  70. startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
  71. stoppt = (unsigned long)&page_table[end];
  72. stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
  73. mmu_page_table_flush(startpt, stoppt);
  74. }
  75. __weak void dram_bank_mmu_setup(int bank)
  76. {
  77. bd_t *bd = gd->bd;
  78. int i;
  79. debug("%s: bank: %d\n", __func__, bank);
  80. for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  81. i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
  82. (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
  83. i++) {
  84. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  85. set_section_dcache(i, DCACHE_WRITETHROUGH);
  86. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  87. set_section_dcache(i, DCACHE_WRITEALLOC);
  88. #else
  89. set_section_dcache(i, DCACHE_WRITEBACK);
  90. #endif
  91. }
  92. }
  93. /* to activate the MMU we need to set up virtual memory: use 1M areas */
  94. static inline void mmu_setup(void)
  95. {
  96. int i;
  97. u32 reg;
  98. arm_init_before_mmu();
  99. /* Set up an identity-mapping for all 4GB, rw for everyone */
  100. for (i = 0; i < ((4096ULL * 1024 * 1024) >> MMU_SECTION_SHIFT); i++)
  101. set_section_dcache(i, DCACHE_OFF);
  102. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  103. dram_bank_mmu_setup(i);
  104. }
  105. #ifdef CONFIG_ARMV7_LPAE
  106. /* Set up 4 PTE entries pointing to our 4 1GB page tables */
  107. for (i = 0; i < 4; i++) {
  108. u64 *page_table = (u64 *)(gd->arch.tlb_addr + (4096 * 4));
  109. u64 tpt = gd->arch.tlb_addr + (4096 * i);
  110. page_table[i] = tpt | TTB_PAGETABLE;
  111. }
  112. reg = TTBCR_EAE;
  113. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  114. reg |= TTBCR_ORGN0_WT | TTBCR_IRGN0_WT;
  115. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  116. reg |= TTBCR_ORGN0_WBWA | TTBCR_IRGN0_WBWA;
  117. #else
  118. reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA;
  119. #endif
  120. if (is_hyp()) {
  121. /* Set HCTR to enable LPAE */
  122. asm volatile("mcr p15, 4, %0, c2, c0, 2"
  123. : : "r" (reg) : "memory");
  124. /* Set HTTBR0 */
  125. asm volatile("mcrr p15, 4, %0, %1, c2"
  126. :
  127. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  128. : "memory");
  129. /* Set HMAIR */
  130. asm volatile("mcr p15, 4, %0, c10, c2, 0"
  131. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  132. } else {
  133. /* Set TTBCR to enable LPAE */
  134. asm volatile("mcr p15, 0, %0, c2, c0, 2"
  135. : : "r" (reg) : "memory");
  136. /* Set 64-bit TTBR0 */
  137. asm volatile("mcrr p15, 0, %0, %1, c2"
  138. :
  139. : "r"(gd->arch.tlb_addr + (4096 * 4)), "r"(0)
  140. : "memory");
  141. /* Set MAIR */
  142. asm volatile("mcr p15, 0, %0, c10, c2, 0"
  143. : : "r" (MEMORY_ATTRIBUTES) : "memory");
  144. }
  145. #elif defined(CONFIG_CPU_V7)
  146. /* Set TTBR0 */
  147. reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
  148. #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
  149. reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
  150. #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
  151. reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
  152. #else
  153. reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
  154. #endif
  155. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  156. : : "r" (reg) : "memory");
  157. #else
  158. /* Copy the page table address to cp15 */
  159. asm volatile("mcr p15, 0, %0, c2, c0, 0"
  160. : : "r" (gd->arch.tlb_addr) : "memory");
  161. #endif
  162. /* Set the access control to all-supervisor */
  163. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  164. : : "r" (~0));
  165. arm_init_domains();
  166. /* and enable the mmu */
  167. reg = get_cr(); /* get control reg. */
  168. cp_delay();
  169. set_cr(reg | CR_M);
  170. }
  171. static int mmu_enabled(void)
  172. {
  173. return get_cr() & CR_M;
  174. }
  175. /* cache_bit must be either CR_I or CR_C */
  176. static void cache_enable(uint32_t cache_bit)
  177. {
  178. uint32_t reg;
  179. /* The data cache is not active unless the mmu is enabled too */
  180. if ((cache_bit == CR_C) && !mmu_enabled())
  181. mmu_setup();
  182. reg = get_cr(); /* get control reg. */
  183. cp_delay();
  184. set_cr(reg | cache_bit);
  185. }
  186. /* cache_bit must be either CR_I or CR_C */
  187. static void cache_disable(uint32_t cache_bit)
  188. {
  189. uint32_t reg;
  190. reg = get_cr();
  191. cp_delay();
  192. if (cache_bit == CR_C) {
  193. /* if cache isn;t enabled no need to disable */
  194. if ((reg & CR_C) != CR_C)
  195. return;
  196. /* if disabling data cache, disable mmu too */
  197. cache_bit |= CR_M;
  198. }
  199. reg = get_cr();
  200. cp_delay();
  201. if (cache_bit == (CR_C | CR_M))
  202. flush_dcache_all();
  203. set_cr(reg & ~cache_bit);
  204. }
  205. #endif
  206. #ifdef CONFIG_SYS_ICACHE_OFF
  207. void icache_enable (void)
  208. {
  209. return;
  210. }
  211. void icache_disable (void)
  212. {
  213. return;
  214. }
  215. int icache_status (void)
  216. {
  217. return 0; /* always off */
  218. }
  219. #else
  220. void icache_enable(void)
  221. {
  222. cache_enable(CR_I);
  223. }
  224. void icache_disable(void)
  225. {
  226. cache_disable(CR_I);
  227. }
  228. int icache_status(void)
  229. {
  230. return (get_cr() & CR_I) != 0;
  231. }
  232. #endif
  233. #ifdef CONFIG_SYS_DCACHE_OFF
  234. void dcache_enable (void)
  235. {
  236. return;
  237. }
  238. void dcache_disable (void)
  239. {
  240. return;
  241. }
  242. int dcache_status (void)
  243. {
  244. return 0; /* always off */
  245. }
  246. #else
  247. void dcache_enable(void)
  248. {
  249. cache_enable(CR_C);
  250. }
  251. void dcache_disable(void)
  252. {
  253. cache_disable(CR_C);
  254. }
  255. int dcache_status(void)
  256. {
  257. return (get_cr() & CR_C) != 0;
  258. }
  259. #endif