Home Explore Help
Sign In
coolsoul
/
u-boot
1
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: 2aa43f70cf
Branches Tags
u-boot
/
arch
/
arm
/
include
/
asm
/
arch-exynos
/
dmc.h

dmc.h 13 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497 
  1. #ifndef __DMC_H__
    2. 

  2. #define __DMC_H__
    3. 

  3. 

  4. #ifndef __ASSEMBLY__
    5. 

  5. struct exynos4_dmc {
    6. 

  6. 	unsigned int concontrol;
    7. 

  7. 	unsigned int memcontrol;
    8. 

  8. 	unsigned int memconfig0;
    9. 

  9. 	unsigned int memconfig1;
    10. 

  10. 	unsigned int directcmd;
    11. 

  11. 	unsigned int prechconfig;
    12. 

  12. 	unsigned int phycontrol0;
    13. 

  13. 	unsigned int phycontrol1;
    14. 

  14. 	unsigned int phycontrol2;
    15. 

  15. 	unsigned int phycontrol3;
    16. 

  16. 	unsigned int pwrdnconfig;
    17. 

  17. 	unsigned char res1[0x4];
    18. 

  18. 	unsigned int timingref;
    19. 

  19. 	unsigned int timingrow;
    20. 

  20. 	unsigned int timingdata;
    21. 

  21. 	unsigned int timingpower;
    22. 

  22. 	unsigned int phystatus;
    23. 

  23. 	unsigned int phyzqcontrol;
    24. 

  24. 	unsigned int chip0status;
    25. 

  25. 	unsigned int chip1status;
    26. 

  26. 	unsigned int arefstatus;
    27. 

  27. 	unsigned int mrstatus;
    28. 

  28. 	unsigned int phytest0;
    29. 

  29. 	unsigned int phytest1;
    30. 

  30. 	unsigned int qoscontrol0;
    31. 

  31. 	unsigned int qosconfig0;
    32. 

  32. 	unsigned int qoscontrol1;
    33. 

  33. 	unsigned int qosconfig1;
    34. 

  34. 	unsigned int qoscontrol2;
    35. 

  35. 	unsigned int qosconfig2;
    36. 

  36. 	unsigned int qoscontrol3;
    37. 

  37. 	unsigned int qosconfig3;
    38. 

  38. 	unsigned int qoscontrol4;
    39. 

  39. 	unsigned int qosconfig4;
    40. 

  40. 	unsigned int qoscontrol5;
    41. 

  41. 	unsigned int qosconfig5;
    42. 

  42. 	unsigned int qoscontrol6;
    43. 

  43. 	unsigned int qosconfig6;
    44. 

  44. 	unsigned int qoscontrol7;
    45. 

  45. 	unsigned int qosconfig7;
    46. 

  46. 	unsigned int qoscontrol8;
    47. 

  47. 	unsigned int qosconfig8;
    48. 

  48. 	unsigned int qoscontrol9;
    49. 

  49. 	unsigned int qosconfig9;
    50. 

  50. 	unsigned int qoscontrol10;
    51. 

  51. 	unsigned int qosconfig10;
    52. 

  52. 	unsigned int qoscontrol11;
    53. 

  53. 	unsigned int qosconfig11;
    54. 

  54. 	unsigned int qoscontrol12;
    55. 

  55. 	unsigned int qosconfig12;
    56. 

  56. 	unsigned int qoscontrol13;
    57. 

  57. 	unsigned int qosconfig13;
    58. 

  58. 	unsigned int qoscontrol14;
    59. 

  59. 	unsigned int qosconfig14;
    60. 

  60. 	unsigned int qoscontrol15;
    61. 

  61. 	unsigned int qosconfig15;
    62. 

  62. 	unsigned int qostimeout0;
    63. 

  63. 	unsigned int qostimeout1;
    64. 

  64. 	unsigned char res2[0x8];
    65. 

  65. 	unsigned int ivcontrol;
    66. 

  66. 	unsigned char res3[0x8];
    67. 

  67. 	unsigned int perevconfig;
    68. 

  68. 	unsigned char res4[0xDF00];
    69. 

  69. 	unsigned int pmnc_ppc_a;
    70. 

  70. 	unsigned char res5[0xC];
    71. 

  71. 	unsigned int cntens_ppc_a;
    72. 

  72. 	unsigned char res6[0xC];
    73. 

  73. 	unsigned int cntenc_ppc_a;
    74. 

  74. 	unsigned char res7[0xC];
    75. 

  75. 	unsigned int intens_ppc_a;
    76. 

  76. 	unsigned char res8[0xC];
    77. 

  77. 	unsigned int intenc_ppc_a;
    78. 

  78. 	unsigned char res9[0xC];
    79. 

  79. 	unsigned int flag_ppc_a;
    80. 

  80. 	unsigned char res10[0xAC];
    81. 

  81. 	unsigned int ccnt_ppc_a;
    82. 

  82. 	unsigned char res11[0xC];
    83. 

  83. 	unsigned int pmcnt0_ppc_a;
    84. 

  84. 	unsigned char res12[0xC];
    85. 

  85. 	unsigned int pmcnt1_ppc_a;
    86. 

  86. 	unsigned char res13[0xC];
    87. 

  87. 	unsigned int pmcnt2_ppc_a;
    88. 

  88. 	unsigned char res14[0xC];
    89. 

  89. 	unsigned int pmcnt3_ppc_a;
    90. 

  90. 	unsigned char res15[0xEBC];
    91. 

  91. 	unsigned int pmnc_ppc_m;
    92. 

  92. 	unsigned char res16[0xC];
    93. 

  93. 	unsigned int cntens_ppc_m;
    94. 

  94. 	unsigned char res17[0xC];
    95. 

  95. 	unsigned int cntenc_ppc_m;
    96. 

  96. 	unsigned char res18[0xC];
    97. 

  97. 	unsigned int intens_ppc_m;
    98. 

  98. 	unsigned char res19[0xC];
    99. 

  99. 	unsigned int intenc_ppc_m;
    100. 

  100. 	unsigned char res20[0xC];
    101. 

  101. 	unsigned int flag_ppc_m;
    102. 

  102. 	unsigned char res21[0xAC];
    103. 

  103. 	unsigned int ccnt_ppc_m;
    104. 

  104. 	unsigned char res22[0xC];
    105. 

  105. 	unsigned int pmcnt0_ppc_m;
    106. 

  106. 	unsigned char res23[0xC];
    107. 

  107. 	unsigned int pmcnt1_ppc_m;
    108. 

  108. 	unsigned char res24[0xC];
    109. 

  109. 	unsigned int pmcnt2_ppc_m;
    110. 

  110. 	unsigned char res25[0xC];
    111. 

  111. 	unsigned int pmcnt3_ppc_m;
    112. 

  112. };
    113. 

  113. 

  114. struct exynos5_dmc {
    115. 

  115. 	unsigned int concontrol;
    116. 

  116. 	unsigned int memcontrol;
    117. 

  117. 	unsigned int memconfig0;
    118. 

  118. 	unsigned int memconfig1;
    119. 

  119. 	unsigned int directcmd;
    120. 

  120. 	unsigned int prechconfig;
    121. 

  121. 	unsigned int phycontrol0;
    122. 

  122. 	unsigned char res1[0xc];
    123. 

  123. 	unsigned int pwrdnconfig;
    124. 

  124. 	unsigned int timingpzq;
    125. 

  125. 	unsigned int timingref;
    126. 

  126. 	unsigned int timingrow;
    127. 

  127. 	unsigned int timingdata;
    128. 

  128. 	unsigned int timingpower;
    129. 

  129. 	unsigned int phystatus;
    130. 

  130. 	unsigned char res2[0x4];
    131. 

  131. 	unsigned int chipstatus_ch0;
    132. 

  132. 	unsigned int chipstatus_ch1;
    133. 

  133. 	unsigned char res3[0x4];
    134. 

  134. 	unsigned int mrstatus;
    135. 

  135. 	unsigned char res4[0x8];
    136. 

  136. 	unsigned int qoscontrol0;
    137. 

  137. 	unsigned char resr5[0x4];
    138. 

  138. 	unsigned int qoscontrol1;
    139. 

  139. 	unsigned char res6[0x4];
    140. 

  140. 	unsigned int qoscontrol2;
    141. 

  141. 	unsigned char res7[0x4];
    142. 

  142. 	unsigned int qoscontrol3;
    143. 

  143. 	unsigned char res8[0x4];
    144. 

  144. 	unsigned int qoscontrol4;
    145. 

  145. 	unsigned char res9[0x4];
    146. 

  146. 	unsigned int qoscontrol5;
    147. 

  147. 	unsigned char res10[0x4];
    148. 

  148. 	unsigned int qoscontrol6;
    149. 

  149. 	unsigned char res11[0x4];
    150. 

  150. 	unsigned int qoscontrol7;
    151. 

  151. 	unsigned char res12[0x4];
    152. 

  152. 	unsigned int qoscontrol8;
    153. 

  153. 	unsigned char res13[0x4];
    154. 

  154. 	unsigned int qoscontrol9;
    155. 

  155. 	unsigned char res14[0x4];
    156. 

  156. 	unsigned int qoscontrol10;
    157. 

  157. 	unsigned char res15[0x4];
    158. 

  158. 	unsigned int qoscontrol11;
    159. 

  159. 	unsigned char res16[0x4];
    160. 

  160. 	unsigned int qoscontrol12;
    161. 

  161. 	unsigned char res17[0x4];
    162. 

  162. 	unsigned int qoscontrol13;
    163. 

  163. 	unsigned char res18[0x4];
    164. 

  164. 	unsigned int qoscontrol14;
    165. 

  165. 	unsigned char res19[0x4];
    166. 

  166. 	unsigned int qoscontrol15;
    167. 

  167. 	unsigned char res20[0x14];
    168. 

  168. 	unsigned int ivcontrol;
    169. 

  169. 	unsigned int wrtra_config;
    170. 

  170. 	unsigned int rdlvl_config;
    171. 

  171. 	unsigned char res21[0x8];
    172. 

  172. 	unsigned int brbrsvconfig;
    173. 

  173. 	unsigned int brbqosconfig;
    174. 

  174. 	unsigned int membaseconfig0;
    175. 

  175. 	unsigned int membaseconfig1;
    176. 

  176. 	unsigned char res22[0xc];
    177. 

  177. 	unsigned int wrlvl_config;
    178. 

  178. 	unsigned char res23[0xc];
    179. 

  179. 	unsigned int perevcontrol;
    180. 

  180. 	unsigned int perev0config;
    181. 

  181. 	unsigned int perev1config;
    182. 

  182. 	unsigned int perev2config;
    183. 

  183. 	unsigned int perev3config;
    184. 

  184. 	unsigned char res24[0xdebc];
    185. 

  185. 	unsigned int pmnc_ppc_a;
    186. 

  186. 	unsigned char res25[0xc];
    187. 

  187. 	unsigned int cntens_ppc_a;
    188. 

  188. 	unsigned char res26[0xc];
    189. 

  189. 	unsigned int cntenc_ppc_a;
    190. 

  190. 	unsigned char res27[0xc];
    191. 

  191. 	unsigned int intens_ppc_a;
    192. 

  192. 	unsigned char res28[0xc];
    193. 

  193. 	unsigned int intenc_ppc_a;
    194. 

  194. 	unsigned char res29[0xc];
    195. 

  195. 	unsigned int flag_ppc_a;
    196. 

  196. 	unsigned char res30[0xac];
    197. 

  197. 	unsigned int ccnt_ppc_a;
    198. 

  198. 	unsigned char res31[0xc];
    199. 

  199. 	unsigned int pmcnt0_ppc_a;
    200. 

  200. 	unsigned char res32[0xc];
    201. 

  201. 	unsigned int pmcnt1_ppc_a;
    202. 

  202. 	unsigned char res33[0xc];
    203. 

  203. 	unsigned int pmcnt2_ppc_a;
    204. 

  204. 	unsigned char res34[0xc];
    205. 

  205. 	unsigned int pmcnt3_ppc_a;
    206. 

  206. };
    207. 

  207. 

  208. struct exynos5420_dmc {
    209. 

  209. 	unsigned int concontrol;
    210. 

  210. 	unsigned int memcontrol;
    211. 

  211. 	unsigned int cgcontrol;
    212. 

  212. 	unsigned char res500[0x4];
    213. 

  213. 	unsigned int directcmd;
    214. 

  214. 	unsigned int prechconfig0;
    215. 

  215. 	unsigned int phycontrol0;
    216. 

  216. 	unsigned int prechconfig1;
    217. 

  217. 	unsigned char res1[0x8];
    218. 

  218. 	unsigned int pwrdnconfig;
    219. 

  219. 	unsigned int timingpzq;
    220. 

  220. 	unsigned int timingref;
    221. 

  221. 	unsigned int timingrow0;
    222. 

  222. 	unsigned int timingdata0;
    223. 

  223. 	unsigned int timingpower0;
    224. 

  224. 	unsigned int phystatus;
    225. 

  225. 	unsigned int etctiming;
    226. 

  226. 	unsigned int chipstatus;
    227. 

  227. 	unsigned char res3[0x8];
    228. 

  228. 	unsigned int mrstatus;
    229. 

  229. 	unsigned char res4[0x8];
    230. 

  230. 	unsigned int qoscontrol0;
    231. 

  231. 	unsigned char resr5[0x4];
    232. 

  232. 	unsigned int qoscontrol1;
    233. 

  233. 	unsigned char res6[0x4];
    234. 

  234. 	unsigned int qoscontrol2;
    235. 

  235. 	unsigned char res7[0x4];
    236. 

  236. 	unsigned int qoscontrol3;
    237. 

  237. 	unsigned char res8[0x4];
    238. 

  238. 	unsigned int qoscontrol4;
    239. 

  239. 	unsigned char res9[0x4];
    240. 

  240. 	unsigned int qoscontrol5;
    241. 

  241. 	unsigned char res10[0x4];
    242. 

  242. 	unsigned int qoscontrol6;
    243. 

  243. 	unsigned char res11[0x4];
    244. 

  244. 	unsigned int qoscontrol7;
    245. 

  245. 	unsigned char res12[0x4];
    246. 

  246. 	unsigned int qoscontrol8;
    247. 

  247. 	unsigned char res13[0x4];
    248. 

  248. 	unsigned int qoscontrol9;
    249. 

  249. 	unsigned char res14[0x4];
    250. 

  250. 	unsigned int qoscontrol10;
    251. 

  251. 	unsigned char res15[0x4];
    252. 

  252. 	unsigned int qoscontrol11;
    253. 

  253. 	unsigned char res16[0x4];
    254. 

  254. 	unsigned int qoscontrol12;
    255. 

  255. 	unsigned char res17[0x4];
    256. 

  256. 	unsigned int qoscontrol13;
    257. 

  257. 	unsigned char res18[0x4];
    258. 

  258. 	unsigned int qoscontrol14;
    259. 

  259. 	unsigned char res19[0x4];
    260. 

  260. 	unsigned int qoscontrol15;
    261. 

  261. 	unsigned char res20[0x4];
    262. 

  262. 	unsigned int timing_set_sw;
    263. 

  263. 	unsigned int timingrow1;
    264. 

  264. 	unsigned int timingdata1;
    265. 

  265. 	unsigned int timingpower1;
    266. 

  266. 	unsigned char res300[0x4];
    267. 

  267. 	unsigned int wrtra_config;
    268. 

  268. 	unsigned int rdlvl_config;
    269. 

  269. 	unsigned char res21[0x4];
    270. 

  270. 	unsigned int brbrsvcontrol;
    271. 

  271. 	unsigned int brbrsvconfig;
    272. 

  272. 	unsigned int brbqosconfig;
    273. 

  273. 	unsigned char res301[0x14];
    274. 

  274. 	unsigned int wrlvl_config0;
    275. 

  275. 	unsigned int wrlvl_config1;
    276. 

  276. 	unsigned int wrlvl_status;
    277. 

  277. 	unsigned char res23[0x4];
    278. 

  278. 	unsigned int ppcclockon;
    279. 

  279. 	unsigned int perevconfig0;
    280. 

  280. 	unsigned int perevconfig1;
    281. 

  281. 	unsigned int perevconfig2;
    282. 

  282. 	unsigned int perevconfig3;
    283. 

  283. 	unsigned char res24[0xc];
    284. 

  284. 	unsigned int control_io_rdata;
    285. 

  285. 	unsigned char res240[0xc];
    286. 

  286. 	unsigned int cacal_config0;
    287. 

  287. 	unsigned int cacal_config1;
    288. 

  288. 	unsigned int cacal_status;
    289. 

  289. 	unsigned char res302[0xa4];
    290. 

  290. 	unsigned int bp_control0;
    291. 

  291. 	unsigned int bp_config0_r;
    292. 

  292. 	unsigned int bp_config0_w;
    293. 

  293. 	unsigned char res303[0x4];
    294. 

  294. 	unsigned int bp_control1;
    295. 

  295. 	unsigned int bp_config1_r;
    296. 

  296. 	unsigned int bp_config1_w;
    297. 

  297. 	unsigned char res304[0x4];
    298. 

  298. 	unsigned int bp_control2;
    299. 

  299. 	unsigned int bp_config2_r;
    300. 

  300. 	unsigned int bp_config2_w;
    301. 

  301. 	unsigned char res305[0x4];
    302. 

  302. 	unsigned int bp_control3;
    303. 

  303. 	unsigned int bp_config3_r;
    304. 

  304. 	unsigned int bp_config3_w;
    305. 

  305. 	unsigned char res306[0xddb4];
    306. 

  306. 	unsigned int pmnc_ppc;
    307. 

  307. 	unsigned char res25[0xc];
    308. 

  308. 	unsigned int cntens_ppc;
    309. 

  309. 	unsigned char res26[0xc];
    310. 

  310. 	unsigned int cntenc_ppc;
    311. 

  311. 	unsigned char res27[0xc];
    312. 

  312. 	unsigned int intens_ppc;
    313. 

  313. 	unsigned char res28[0xc];
    314. 

  314. 	unsigned int intenc_ppc;
    315. 

  315. 	unsigned char res29[0xc];
    316. 

  316. 	unsigned int flag_ppc;
    317. 

  317. 	unsigned char res30[0xac];
    318. 

  318. 	unsigned int ccnt_ppc;
    319. 

  319. 	unsigned char res31[0xc];
    320. 

  320. 	unsigned int pmcnt0_ppc;
    321. 

  321. 	unsigned char res32[0xc];
    322. 

  322. 	unsigned int pmcnt1_ppc;
    323. 

  323. 	unsigned char res33[0xc];
    324. 

  324. 	unsigned int pmcnt2_ppc;
    325. 

  325. 	unsigned char res34[0xc];
    326. 

  326. 	unsigned int pmcnt3_ppc;
    327. 

  327. };
    328. 

  328. 

  329. struct exynos5_phy_control {
    330. 

  330. 	unsigned int phy_con0;
    331. 

  331. 	unsigned int phy_con1;
    332. 

  332. 	unsigned int phy_con2;
    333. 

  333. 	unsigned int phy_con3;
    334. 

  334. 	unsigned int phy_con4;
    335. 

  335. 	unsigned char res1[4];
    336. 

  336. 	unsigned int phy_con6;
    337. 

  337. 	unsigned char res2[4];
    338. 

  338. 	unsigned int phy_con8;
    339. 

  339. 	unsigned int phy_con9;
    340. 

  340. 	unsigned int phy_con10;
    341. 

  341. 	unsigned char res3[4];
    342. 

  342. 	unsigned int phy_con12;
    343. 

  343. 	unsigned int phy_con13;
    344. 

  344. 	unsigned int phy_con14;
    345. 

  345. 	unsigned int phy_con15;
    346. 

  346. 	unsigned int phy_con16;
    347. 

  347. 	unsigned char res4[4];
    348. 

  348. 	unsigned int phy_con17;
    349. 

  349. 	unsigned int phy_con18;
    350. 

  350. 	unsigned int phy_con19;
    351. 

  351. 	unsigned int phy_con20;
    352. 

  352. 	unsigned int phy_con21;
    353. 

  353. 	unsigned int phy_con22;
    354. 

  354. 	unsigned int phy_con23;
    355. 

  355. 	unsigned int phy_con24;
    356. 

  356. 	unsigned int phy_con25;
    357. 

  357. 	unsigned int phy_con26;
    358. 

  358. 	unsigned int phy_con27;
    359. 

  359. 	unsigned int phy_con28;
    360. 

  360. 	unsigned int phy_con29;
    361. 

  361. 	unsigned int phy_con30;
    362. 

  362. 	unsigned int phy_con31;
    363. 

  363. 	unsigned int phy_con32;
    364. 

  364. 	unsigned int phy_con33;
    365. 

  365. 	unsigned int phy_con34;
    366. 

  366. 	unsigned int phy_con35;
    367. 

  367. 	unsigned int phy_con36;
    368. 

  368. 	unsigned int phy_con37;
    369. 

  369. 	unsigned int phy_con38;
    370. 

  370. 	unsigned int phy_con39;
    371. 

  371. 	unsigned int phy_con40;
    372. 

  372. 	unsigned int phy_con41;
    373. 

  373. 	unsigned int phy_con42;
    374. 

  374. };
    375. 

  375. 

  376. struct exynos5420_phy_control {
    377. 

  377. 	unsigned int phy_con0;
    378. 

  378. 	unsigned int phy_con1;
    379. 

  379. 	unsigned int phy_con2;
    380. 

  380. 	unsigned int phy_con3;
    381. 

  381. 	unsigned int phy_con4;
    382. 

  382. 	unsigned int phy_con5;
    383. 

  383. 	unsigned int phy_con6;
    384. 

  384. 	unsigned char res2[0x4];
    385. 

  385. 	unsigned int phy_con8;
    386. 

  386. 	unsigned char res5[0x4];
    387. 

  387. 	unsigned int phy_con10;
    388. 

  388. 	unsigned int phy_con11;
    389. 

  389. 	unsigned int phy_con12;
    390. 

  390. 	unsigned int phy_con13;
    391. 

  391. 	unsigned int phy_con14;
    392. 

  392. 	unsigned int phy_con15;
    393. 

  393. 	unsigned int phy_con16;
    394. 

  394. 	unsigned char res4[0x4];
    395. 

  395. 	unsigned int phy_con17;
    396. 

  396. 	unsigned int phy_con18;
    397. 

  397. 	unsigned int phy_con19;
    398. 

  398. 	unsigned int phy_con20;
    399. 

  399. 	unsigned int phy_con21;
    400. 

  400. 	unsigned int phy_con22;
    401. 

  401. 	unsigned int phy_con23;
    402. 

  402. 	unsigned int phy_con24;
    403. 

  403. 	unsigned int phy_con25;
    404. 

  404. 	unsigned int phy_con26;
    405. 

  405. 	unsigned int phy_con27;
    406. 

  406. 	unsigned int phy_con28;
    407. 

  407. 	unsigned int phy_con29;
    408. 

  408. 	unsigned int phy_con30;
    409. 

  409. 	unsigned int phy_con31;
    410. 

  410. 	unsigned int phy_con32;
    411. 

  411. 	unsigned int phy_con33;
    412. 

  412. 	unsigned int phy_con34;
    413. 

  413. 	unsigned char res6[0x8];
    414. 

  414. 	unsigned int phy_con37;
    415. 

  415. 	unsigned char res7[0x4];
    416. 

  416. 	unsigned int phy_con39;
    417. 

  417. 	unsigned int phy_con40;
    418. 

  418. 	unsigned int phy_con41;
    419. 

  419. 	unsigned int phy_con42;
    420. 

  420. };
    421. 

  421. 

  422. struct exynos5420_tzasc {
    423. 

  423. 	unsigned char res1[0xf00];
    424. 

  424. 	unsigned int membaseconfig0;
    425. 

  425. 	unsigned int membaseconfig1;
    426. 

  426. 	unsigned char res2[0x8];
    427. 

  427. 	unsigned int memconfig0;
    428. 

  428. 	unsigned int memconfig1;
    429. 

  429. };
    430. 

  430. 

  431. enum ddr_mode {
    432. 

  432. 	DDR_MODE_DDR2,
    433. 

  433. 	DDR_MODE_DDR3,
    434. 

  434. 	DDR_MODE_LPDDR2,
    435. 

  435. 	DDR_MODE_LPDDR3,
    436. 

  436. 

  437. 	DDR_MODE_COUNT,
    438. 

  438. };
    439. 

  439. 

  440. enum mem_manuf {
    441. 

  441. 	MEM_MANUF_AUTODETECT,
    442. 

  442. 	MEM_MANUF_ELPIDA,
    443. 

  443. 	MEM_MANUF_SAMSUNG,
    444. 

  444. 

  445. 	MEM_MANUF_COUNT,
    446. 

  446. };
    447. 

  447. 

  448. /* CONCONTROL register fields */
    449. 

  449. #define CONCONTROL_DFI_INIT_START_SHIFT	28
    450. 

  450. #define CONCONTROL_RD_FETCH_SHIFT	12
    451. 

  451. #define CONCONTROL_RD_FETCH_MASK	(0x7 << CONCONTROL_RD_FETCH_SHIFT)
    452. 

  452. #define CONCONTROL_AREF_EN_SHIFT	5
    453. 

  453. 

  454. /* PRECHCONFIG register field */
    455. 

  455. #define PRECHCONFIG_TP_CNT_SHIFT	24
    456. 

  456. 

  457. /* PWRDNCONFIG register field */
    458. 

  458. #define PWRDNCONFIG_DPWRDN_CYC_SHIFT	0
    459. 

  459. #define PWRDNCONFIG_DSREF_CYC_SHIFT	16
    460. 

  460. 

  461. /* PHY_CON0 register fields */
    462. 

  462. #define PHY_CON0_T_WRRDCMD_SHIFT	17
    463. 

  463. #define PHY_CON0_T_WRRDCMD_MASK		(0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
    464. 

  464. #define PHY_CON0_CTRL_DDR_MODE_SHIFT	11
    465. 

  465. #define PHY_CON0_CTRL_DDR_MODE_MASK	0x3
    466. 

  466. 

  467. /* PHY_CON1 register fields */
    468. 

  468. #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT	0
    469. 

  469. 

  470. /* PHY_CON12 register fields */
    471. 

  471. #define PHY_CON12_CTRL_START_POINT_SHIFT	24
    472. 

  472. #define PHY_CON12_CTRL_INC_SHIFT	16
    473. 

  473. #define PHY_CON12_CTRL_FORCE_SHIFT	8
    474. 

  474. #define PHY_CON12_CTRL_START_SHIFT	6
    475. 

  475. #define PHY_CON12_CTRL_START_MASK	(1 << PHY_CON12_CTRL_START_SHIFT)
    476. 

  476. #define PHY_CON12_CTRL_DLL_ON_SHIFT	5
    477. 

  477. #define PHY_CON12_CTRL_DLL_ON_MASK	(1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
    478. 

  478. #define PHY_CON12_CTRL_REF_SHIFT	1
    479. 

  479. 

  480. /* PHY_CON16 register fields */
    481. 

  481. #define PHY_CON16_ZQ_MODE_DDS_SHIFT	24
    482. 

  482. #define PHY_CON16_ZQ_MODE_DDS_MASK	(0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
    483. 

  483. 

  484. #define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
    485. 

  485. #define PHY_CON16_ZQ_MODE_TERM_MASK	(0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
    486. 

  486. 

  487. #define PHY_CON16_ZQ_MODE_NOTERM_MASK	(1 << 19)
    488. 

  488. 

  489. /* PHY_CON42 register fields */
    490. 

  490. #define PHY_CON42_CTRL_BSTLEN_SHIFT	8
    491. 

  491. #define PHY_CON42_CTRL_BSTLEN_MASK	(0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
    492. 

  492. 

  493. #define PHY_CON42_CTRL_RDLAT_SHIFT	0
    494. 

  494. #define PHY_CON42_CTRL_RDLAT_MASK	(0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
    495. 

  495. 

  496. #endif
    497. 

  497. #endif
    498.