at91sam9_wdt.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
  4. *
  5. * Watchdog driver for Atmel AT91SAM9x processors.
  6. *
  7. * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  8. * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
  9. */
  10. /*
  11. * The Watchdog Timer Mode Register can be only written to once. If the
  12. * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
  13. * write to this register. Inform Linux to it too
  14. */
  15. #include <common.h>
  16. #include <watchdog.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/at91_wdt.h>
  20. /*
  21. * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
  22. * use this to convert a watchdog
  23. * value from/to milliseconds.
  24. */
  25. #define ms_to_ticks(t) (((t << 8) / 1000) - 1)
  26. #define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
  27. /* Hardware timeout in seconds */
  28. #if !defined(CONFIG_AT91_HW_WDT_TIMEOUT)
  29. #define WDT_HW_TIMEOUT 2
  30. #else
  31. #define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT
  32. #endif
  33. /*
  34. * Set the watchdog time interval in 1/256Hz (write-once)
  35. * Counter is 12 bit.
  36. */
  37. static int at91_wdt_settimeout(unsigned int timeout)
  38. {
  39. unsigned int reg;
  40. at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
  41. /* Check if disabled */
  42. if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) {
  43. printf("sorry, watchdog is disabled\n");
  44. return -1;
  45. }
  46. /*
  47. * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
  48. *
  49. * Since WDV is a 12-bit counter, the maximum period is
  50. * 4096 / 256 = 16 seconds.
  51. */
  52. reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
  53. | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
  54. | AT91_WDT_MR_WDD(0xfff) /* restart at any time */
  55. | AT91_WDT_MR_WDV(timeout); /* timer value */
  56. writel(reg, &wd->mr);
  57. return 0;
  58. }
  59. void hw_watchdog_reset(void)
  60. {
  61. at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
  62. writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr);
  63. }
  64. void hw_watchdog_init(void)
  65. {
  66. /* 16 seconds timer, resets enabled */
  67. at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
  68. }