pcf8575_gpio.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCF8575 I2C GPIO EXPANDER DRIVER
  4. *
  5. * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
  6. *
  7. * Vignesh R <vigneshr@ti.com>
  8. *
  9. *
  10. * Driver for TI PCF-8575 16-bit I2C gpio expander. Based on
  11. * gpio-pcf857x Linux Kernel(v4.7) driver.
  12. *
  13. * Copyright (C) 2007 David Brownell
  14. *
  15. */
  16. /*
  17. * NOTE: The driver and devicetree bindings are borrowed from Linux
  18. * Kernel, but driver does not support all PCF857x devices. It currently
  19. * supports PCF8575 16-bit expander by TI and NXP.
  20. *
  21. * TODO(vigneshr@ti.com):
  22. * Support 8 bit PCF857x compatible expanders.
  23. */
  24. #include <common.h>
  25. #include <dm.h>
  26. #include <i2c.h>
  27. #include <asm-generic/gpio.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. struct pcf8575_chip {
  30. int gpio_count; /* No. GPIOs supported by the chip */
  31. /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
  32. * We can't actually know whether a pin is configured (a) as output
  33. * and driving the signal low, or (b) as input and reporting a low
  34. * value ... without knowing the last value written since the chip
  35. * came out of reset (if any). We can't read the latched output.
  36. * In short, the only reliable solution for setting up pin direction
  37. * is to do it explicitly.
  38. *
  39. * Using "out" avoids that trouble. When left initialized to zero,
  40. * our software copy of the "latch" then matches the chip's all-ones
  41. * reset state. Otherwise it flags pins to be driven low.
  42. */
  43. unsigned int out; /* software latch */
  44. const char *bank_name; /* Name of the expander bank */
  45. };
  46. /* Read/Write to 16-bit I/O expander */
  47. static int pcf8575_i2c_write_le16(struct udevice *dev, unsigned int word)
  48. {
  49. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  50. u8 buf[2] = { word & 0xff, word >> 8, };
  51. int ret;
  52. ret = dm_i2c_write(dev, 0, buf, 2);
  53. if (ret)
  54. printf("%s i2c write failed to addr %x\n", __func__,
  55. chip->chip_addr);
  56. return ret;
  57. }
  58. static int pcf8575_i2c_read_le16(struct udevice *dev)
  59. {
  60. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  61. u8 buf[2];
  62. int ret;
  63. ret = dm_i2c_read(dev, 0, buf, 2);
  64. if (ret) {
  65. printf("%s i2c read failed from addr %x\n", __func__,
  66. chip->chip_addr);
  67. return ret;
  68. }
  69. return (buf[1] << 8) | buf[0];
  70. }
  71. static int pcf8575_direction_input(struct udevice *dev, unsigned offset)
  72. {
  73. struct pcf8575_chip *plat = dev_get_platdata(dev);
  74. int status;
  75. plat->out |= BIT(offset);
  76. status = pcf8575_i2c_write_le16(dev, plat->out);
  77. return status;
  78. }
  79. static int pcf8575_direction_output(struct udevice *dev,
  80. unsigned int offset, int value)
  81. {
  82. struct pcf8575_chip *plat = dev_get_platdata(dev);
  83. int ret;
  84. if (value)
  85. plat->out |= BIT(offset);
  86. else
  87. plat->out &= ~BIT(offset);
  88. ret = pcf8575_i2c_write_le16(dev, plat->out);
  89. return ret;
  90. }
  91. static int pcf8575_get_value(struct udevice *dev, unsigned int offset)
  92. {
  93. int value;
  94. value = pcf8575_i2c_read_le16(dev);
  95. return (value < 0) ? value : ((value & BIT(offset)) >> offset);
  96. }
  97. static int pcf8575_set_value(struct udevice *dev, unsigned int offset,
  98. int value)
  99. {
  100. return pcf8575_direction_output(dev, offset, value);
  101. }
  102. static int pcf8575_ofdata_platdata(struct udevice *dev)
  103. {
  104. struct pcf8575_chip *plat = dev_get_platdata(dev);
  105. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  106. int n_latch;
  107. uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  108. "gpio-count", 16);
  109. uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  110. "gpio-bank-name", NULL);
  111. if (!uc_priv->bank_name)
  112. uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
  113. dev_of_offset(dev), NULL);
  114. n_latch = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  115. "lines-initial-states", 0);
  116. plat->out = ~n_latch;
  117. return 0;
  118. }
  119. static int pcf8575_gpio_probe(struct udevice *dev)
  120. {
  121. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  122. debug("%s GPIO controller with %d gpios probed\n",
  123. uc_priv->bank_name, uc_priv->gpio_count);
  124. return 0;
  125. }
  126. static const struct dm_gpio_ops pcf8575_gpio_ops = {
  127. .direction_input = pcf8575_direction_input,
  128. .direction_output = pcf8575_direction_output,
  129. .get_value = pcf8575_get_value,
  130. .set_value = pcf8575_set_value,
  131. };
  132. static const struct udevice_id pcf8575_gpio_ids[] = {
  133. { .compatible = "nxp,pcf8575" },
  134. { .compatible = "ti,pcf8575" },
  135. { }
  136. };
  137. U_BOOT_DRIVER(gpio_pcf8575) = {
  138. .name = "gpio_pcf8575",
  139. .id = UCLASS_GPIO,
  140. .ops = &pcf8575_gpio_ops,
  141. .of_match = pcf8575_gpio_ids,
  142. .ofdata_to_platdata = pcf8575_ofdata_platdata,
  143. .probe = pcf8575_gpio_probe,
  144. .platdata_auto_alloc_size = sizeof(struct pcf8575_chip),
  145. };