irq.h 1.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. */
  5. #ifndef _ARCH_IRQ_H_
  6. #define _ARCH_IRQ_H_
  7. #include <dt-bindings/interrupt-router/intel-irq.h>
  8. /**
  9. * Intel interrupt router configuration mechanism
  10. *
  11. * There are two known ways of Intel interrupt router configuration mechanism
  12. * so far. On most cases, the IRQ routing configuraiton is controlled by PCI
  13. * configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
  14. * On some newer platforms like BayTrail and Braswell, the IRQ routing is now
  15. * in the IBASE register block where IBASE is memory-mapped.
  16. */
  17. enum pirq_config {
  18. PIRQ_VIA_PCI,
  19. PIRQ_VIA_IBASE
  20. };
  21. struct pirq_regmap {
  22. int link;
  23. int offset;
  24. };
  25. /**
  26. * Intel interrupt router control block
  27. *
  28. * Its members' value will be filled in based on device tree's input.
  29. *
  30. * @config: PIRQ_VIA_PCI or PIRQ_VIA_IBASE
  31. * @link_base: link value base number
  32. * @link_num: number of PIRQ links supported
  33. * @has_regmap: has mapping table between PIRQ link and routing register offset
  34. * @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
  35. * IRQ N is available to be routed
  36. * @lb_bdf: irq router's PCI bus/device/function number encoding
  37. * @ibase: IBASE register block base address
  38. * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset)
  39. * @actl_addr: ACTL register offset
  40. */
  41. struct irq_router {
  42. int config;
  43. u32 link_base;
  44. int link_num;
  45. bool has_regmap;
  46. struct pirq_regmap *regmap;
  47. u16 irq_mask;
  48. u32 bdf;
  49. u32 ibase;
  50. bool actl_8bit;
  51. int actl_addr;
  52. };
  53. struct pirq_routing {
  54. int bdf;
  55. int pin;
  56. int pirq;
  57. };
  58. #define PIRQ_BITMAP 0xdef8
  59. #endif /* _ARCH_IRQ_H_ */