i8254.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2002
  4. * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
  5. */
  6. /* i8254.h Intel 8254 PIT registers */
  7. #ifndef _ASMI386_I8254_H_
  8. #define _ASMI386_I8954_H_
  9. #define PIT_T0 0x00 /* PIT channel 0 count/status */
  10. #define PIT_T1 0x01 /* PIT channel 1 count/status */
  11. #define PIT_T2 0x02 /* PIT channel 2 count/status */
  12. #define PIT_COMMAND 0x03 /* PIT mode control, latch and read back */
  13. /* PIT Command Register Bit Definitions */
  14. #define PIT_CMD_CTR0 0x00 /* Select PIT counter 0 */
  15. #define PIT_CMD_CTR1 0x40 /* Select PIT counter 1 */
  16. #define PIT_CMD_CTR2 0x80 /* Select PIT counter 2 */
  17. #define PIT_CMD_LATCH 0x00 /* Counter Latch Command */
  18. #define PIT_CMD_LOW 0x10 /* Access counter bits 7-0 */
  19. #define PIT_CMD_HIGH 0x20 /* Access counter bits 15-8 */
  20. #define PIT_CMD_BOTH 0x30 /* Access counter bits 15-0 in two accesses */
  21. #define PIT_CMD_MODE0 0x00 /* Select mode 0 */
  22. #define PIT_CMD_MODE1 0x02 /* Select mode 1 */
  23. #define PIT_CMD_MODE2 0x04 /* Select mode 2 */
  24. #define PIT_CMD_MODE3 0x06 /* Select mode 3 */
  25. #define PIT_CMD_MODE4 0x08 /* Select mode 4 */
  26. #define PIT_CMD_MODE5 0x0a /* Select mode 5 */
  27. /* The clock frequency of the i8253/i8254 PIT */
  28. #define PIT_TICK_RATE 1193182
  29. #endif /* _ASMI386_I8954_H_ */