model_206ax.h 1.9 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * From Coreboot file of the same name
  4. *
  5. * Copyright (C) 2011 The ChromiumOS Authors.
  6. */
  7. #ifndef _ASM_ARCH_MODEL_206AX_H
  8. #define _ASM_ARCH_MODEL_206AX_H
  9. /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
  10. #define SANDYBRIDGE_BCLK 100
  11. #define CPUID_VMX (1 << 5)
  12. #define CPUID_SMX (1 << 6)
  13. #define MSR_FEATURE_CONFIG 0x13c
  14. #define IA32_PLATFORM_DCA_CAP 0x1f8
  15. #define IA32_MISC_ENABLE 0x1a0
  16. #define MSR_TEMPERATURE_TARGET 0x1a2
  17. #define IA32_THERM_INTERRUPT 0x19b
  18. #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
  19. #define ENERGY_POLICY_PERFORMANCE 0
  20. #define ENERGY_POLICY_NORMAL 6
  21. #define ENERGY_POLICY_POWERSAVE 15
  22. #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
  23. #define MSR_LT_LOCK_MEMORY 0x2e7
  24. #define IA32_MC0_STATUS 0x401
  25. #define MSR_MISC_PWR_MGMT 0x1aa
  26. #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
  27. #define MSR_PKGC3_IRTL 0x60a
  28. #define MSR_PKGC6_IRTL 0x60b
  29. #define MSR_PKGC7_IRTL 0x60c
  30. #define IRTL_VALID (1 << 15)
  31. #define IRTL_1_NS (0 << 10)
  32. #define IRTL_32_NS (1 << 10)
  33. #define IRTL_1024_NS (2 << 10)
  34. #define IRTL_32768_NS (3 << 10)
  35. #define IRTL_1048576_NS (4 << 10)
  36. #define IRTL_33554432_NS (5 << 10)
  37. #define IRTL_RESPONSE_MASK (0x3ff)
  38. #define MSR_PP0_CURRENT_CONFIG 0x601
  39. #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
  40. #define MSR_PP1_CURRENT_CONFIG 0x602
  41. #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
  42. #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
  43. #define MSR_PKG_POWER_SKU 0x614
  44. #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
  45. #define MSR_CONFIG_TDP_LEVEL1 0x649
  46. #define MSR_CONFIG_TDP_LEVEL2 0x64a
  47. #define MSR_CONFIG_TDP_CONTROL 0x64b
  48. /* P-state configuration */
  49. #define PSS_MAX_ENTRIES 8
  50. #define PSS_RATIO_STEP 2
  51. #define PSS_LATENCY_TRANSITION 10
  52. #define PSS_LATENCY_BUSMASTER 10
  53. /* Configure power limits for turbo mode */
  54. void set_power_limits(u8 power_limit_1_time);
  55. int cpu_config_tdp_levels(void);
  56. #endif