socfpga_cyclone5.dtsi 662 B

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  1. /*
  2. * Copyright (C) 2012 Altera Corporation <www.altera.com>
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. /dts-v1/;
  7. /* First 4KB has trampoline code for secondary cores. */
  8. /memreserve/ 0x00000000 0x0001000;
  9. #include "socfpga.dtsi"
  10. / {
  11. soc {
  12. clkmgr@ffd04000 {
  13. clocks {
  14. osc1 {
  15. clock-frequency = <25000000>;
  16. };
  17. };
  18. };
  19. mmc0: dwmmc0@ff704000 {
  20. num-slots = <1>;
  21. broken-cd;
  22. bus-width = <4>;
  23. cap-mmc-highspeed;
  24. cap-sd-highspeed;
  25. };
  26. ethernet@ff702000 {
  27. phy-mode = "rgmii";
  28. phy-addr = <0xffffffff>; /* probe for phy addr */
  29. status = "okay";
  30. };
  31. sysmgr@ffd08000 {
  32. cpu1-start-addr = <0xffd080c4>;
  33. };
  34. };
  35. };