mxc_i2c.c 9.1 KB

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  1. /*
  2. * i2c driver for Freescale i.MX series
  3. *
  4. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  5. * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on i2c-imx.c from linux kernel:
  8. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
  9. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  10. * Copyright (C) 2007 RightHand Technologies, Inc.
  11. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  12. *
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. */
  32. #include <common.h>
  33. #include <asm/arch/clock.h>
  34. #include <asm/arch/imx-regs.h>
  35. #include <asm/io.h>
  36. #include <i2c.h>
  37. struct mxc_i2c_regs {
  38. uint32_t iadr;
  39. uint32_t ifdr;
  40. uint32_t i2cr;
  41. uint32_t i2sr;
  42. uint32_t i2dr;
  43. };
  44. #define I2CR_IEN (1 << 7)
  45. #define I2CR_IIEN (1 << 6)
  46. #define I2CR_MSTA (1 << 5)
  47. #define I2CR_MTX (1 << 4)
  48. #define I2CR_TX_NO_AK (1 << 3)
  49. #define I2CR_RSTA (1 << 2)
  50. #define I2SR_ICF (1 << 7)
  51. #define I2SR_IBB (1 << 5)
  52. #define I2SR_IIF (1 << 1)
  53. #define I2SR_RX_NO_AK (1 << 0)
  54. #ifdef CONFIG_SYS_I2C_BASE
  55. #define I2C_BASE CONFIG_SYS_I2C_BASE
  56. #else
  57. #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver"
  58. #endif
  59. #define I2C_MAX_TIMEOUT 10000
  60. static u16 i2c_clk_div[50][2] = {
  61. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  62. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  63. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  64. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  65. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  66. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  67. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  68. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  69. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  70. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  71. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  72. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  73. { 3072, 0x1E }, { 3840, 0x1F }
  74. };
  75. /*
  76. * Calculate and set proper clock divider
  77. */
  78. static uint8_t i2c_imx_get_clk(unsigned int rate)
  79. {
  80. unsigned int i2c_clk_rate;
  81. unsigned int div;
  82. u8 clk_div;
  83. #if defined(CONFIG_MX31)
  84. struct clock_control_regs *sc_regs =
  85. (struct clock_control_regs *)CCM_BASE;
  86. /* start the required I2C clock */
  87. writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
  88. &sc_regs->cgr0);
  89. #endif
  90. /* Divider value calculation */
  91. i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
  92. div = (i2c_clk_rate + rate - 1) / rate;
  93. if (div < i2c_clk_div[0][0])
  94. clk_div = 0;
  95. else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
  96. clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
  97. else
  98. for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
  99. ;
  100. /* Store divider value */
  101. return clk_div;
  102. }
  103. /*
  104. * Reset I2C Controller
  105. */
  106. void i2c_reset(void)
  107. {
  108. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  109. writeb(0, &i2c_regs->i2cr); /* Reset module */
  110. writeb(0, &i2c_regs->i2sr);
  111. }
  112. /*
  113. * Init I2C Bus
  114. */
  115. void i2c_init(int speed, int unused)
  116. {
  117. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  118. u8 clk_idx = i2c_imx_get_clk(speed);
  119. u8 idx = i2c_clk_div[clk_idx][1];
  120. /* Store divider value */
  121. writeb(idx, &i2c_regs->ifdr);
  122. i2c_reset();
  123. }
  124. /*
  125. * Set I2C Speed
  126. */
  127. int i2c_set_bus_speed(unsigned int speed)
  128. {
  129. i2c_init(speed, 0);
  130. return 0;
  131. }
  132. /*
  133. * Get I2C Speed
  134. */
  135. unsigned int i2c_get_bus_speed(void)
  136. {
  137. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  138. u8 clk_idx = readb(&i2c_regs->ifdr);
  139. u8 clk_div;
  140. for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
  141. ;
  142. return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
  143. }
  144. /*
  145. * Wait for bus to be busy (or free if for_busy = 0)
  146. *
  147. * for_busy = 1: Wait for IBB to be asserted
  148. * for_busy = 0: Wait for IBB to be de-asserted
  149. */
  150. int i2c_imx_bus_busy(int for_busy)
  151. {
  152. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  153. unsigned int temp;
  154. int timeout = I2C_MAX_TIMEOUT;
  155. while (timeout--) {
  156. temp = readb(&i2c_regs->i2sr);
  157. if (for_busy && (temp & I2SR_IBB))
  158. return 0;
  159. if (!for_busy && !(temp & I2SR_IBB))
  160. return 0;
  161. udelay(1);
  162. }
  163. return 1;
  164. }
  165. /*
  166. * Wait for transaction to complete
  167. */
  168. int i2c_imx_trx_complete(void)
  169. {
  170. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  171. int timeout = I2C_MAX_TIMEOUT;
  172. while (timeout--) {
  173. if (readb(&i2c_regs->i2sr) & I2SR_IIF) {
  174. writeb(0, &i2c_regs->i2sr);
  175. return 0;
  176. }
  177. udelay(1);
  178. }
  179. return 1;
  180. }
  181. /*
  182. * Check if the transaction was ACKed
  183. */
  184. int i2c_imx_acked(void)
  185. {
  186. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  187. return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK;
  188. }
  189. /*
  190. * Start the controller
  191. */
  192. int i2c_imx_start(void)
  193. {
  194. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  195. unsigned int temp = 0;
  196. int result;
  197. /* Enable I2C controller */
  198. writeb(0, &i2c_regs->i2sr);
  199. writeb(I2CR_IEN, &i2c_regs->i2cr);
  200. /* Wait controller to be stable */
  201. udelay(50);
  202. /* Start I2C transaction */
  203. temp = readb(&i2c_regs->i2cr);
  204. temp |= I2CR_MSTA;
  205. writeb(temp, &i2c_regs->i2cr);
  206. result = i2c_imx_bus_busy(1);
  207. if (result)
  208. return result;
  209. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  210. writeb(temp, &i2c_regs->i2cr);
  211. return 0;
  212. }
  213. /*
  214. * Stop the controller
  215. */
  216. void i2c_imx_stop(void)
  217. {
  218. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  219. unsigned int temp = 0;
  220. /* Stop I2C transaction */
  221. temp = readb(&i2c_regs->i2cr);
  222. temp &= ~(I2CR_MSTA | I2CR_MTX);
  223. writeb(temp, &i2c_regs->i2cr);
  224. i2c_imx_bus_busy(0);
  225. /* Disable I2C controller */
  226. writeb(0, &i2c_regs->i2cr);
  227. }
  228. /*
  229. * Set chip address and access mode
  230. *
  231. * read = 1: READ access
  232. * read = 0: WRITE access
  233. */
  234. int i2c_imx_set_chip_addr(uchar chip, int read)
  235. {
  236. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  237. int ret;
  238. writeb((chip << 1) | read, &i2c_regs->i2dr);
  239. ret = i2c_imx_trx_complete();
  240. if (ret)
  241. return ret;
  242. ret = i2c_imx_acked();
  243. if (ret)
  244. return ret;
  245. return ret;
  246. }
  247. /*
  248. * Write register address
  249. */
  250. int i2c_imx_set_reg_addr(uint addr, int alen)
  251. {
  252. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  253. int ret = 0;
  254. while (alen--) {
  255. writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr);
  256. ret = i2c_imx_trx_complete();
  257. if (ret)
  258. break;
  259. ret = i2c_imx_acked();
  260. if (ret)
  261. break;
  262. }
  263. return ret;
  264. }
  265. /*
  266. * Try if a chip add given address responds (probe the chip)
  267. */
  268. int i2c_probe(uchar chip)
  269. {
  270. int ret;
  271. ret = i2c_imx_start();
  272. if (ret)
  273. return ret;
  274. ret = i2c_imx_set_chip_addr(chip, 0);
  275. if (ret)
  276. return ret;
  277. i2c_imx_stop();
  278. return ret;
  279. }
  280. /*
  281. * Read data from I2C device
  282. */
  283. int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
  284. {
  285. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  286. int ret;
  287. unsigned int temp;
  288. int i;
  289. ret = i2c_imx_start();
  290. if (ret)
  291. return ret;
  292. /* write slave address */
  293. ret = i2c_imx_set_chip_addr(chip, 0);
  294. if (ret)
  295. return ret;
  296. ret = i2c_imx_set_reg_addr(addr, alen);
  297. if (ret)
  298. return ret;
  299. temp = readb(&i2c_regs->i2cr);
  300. temp |= I2CR_RSTA;
  301. writeb(temp, &i2c_regs->i2cr);
  302. ret = i2c_imx_set_chip_addr(chip, 1);
  303. if (ret)
  304. return ret;
  305. /* setup bus to read data */
  306. temp = readb(&i2c_regs->i2cr);
  307. temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
  308. if (len == 1)
  309. temp |= I2CR_TX_NO_AK;
  310. writeb(temp, &i2c_regs->i2cr);
  311. readb(&i2c_regs->i2dr);
  312. /* read data */
  313. for (i = 0; i < len; i++) {
  314. ret = i2c_imx_trx_complete();
  315. if (ret)
  316. return ret;
  317. /*
  318. * It must generate STOP before read I2DR to prevent
  319. * controller from generating another clock cycle
  320. */
  321. if (i == (len - 1)) {
  322. temp = readb(&i2c_regs->i2cr);
  323. temp &= ~(I2CR_MSTA | I2CR_MTX);
  324. writeb(temp, &i2c_regs->i2cr);
  325. i2c_imx_bus_busy(0);
  326. } else if (i == (len - 2)) {
  327. temp = readb(&i2c_regs->i2cr);
  328. temp |= I2CR_TX_NO_AK;
  329. writeb(temp, &i2c_regs->i2cr);
  330. }
  331. buf[i] = readb(&i2c_regs->i2dr);
  332. }
  333. i2c_imx_stop();
  334. return ret;
  335. }
  336. /*
  337. * Write data to I2C device
  338. */
  339. int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
  340. {
  341. struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE;
  342. int ret;
  343. int i;
  344. ret = i2c_imx_start();
  345. if (ret)
  346. return ret;
  347. /* write slave address */
  348. ret = i2c_imx_set_chip_addr(chip, 0);
  349. if (ret)
  350. return ret;
  351. ret = i2c_imx_set_reg_addr(addr, alen);
  352. if (ret)
  353. return ret;
  354. for (i = 0; i < len; i++) {
  355. writeb(buf[i], &i2c_regs->i2dr);
  356. ret = i2c_imx_trx_complete();
  357. if (ret)
  358. return ret;
  359. ret = i2c_imx_acked();
  360. if (ret)
  361. return ret;
  362. }
  363. i2c_imx_stop();
  364. return ret;
  365. }