pci_ftpci100.h 2.6 KB

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  1. /*
  2. * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
  3. *
  4. * Copyright (C) 2010 Andes Technology Corporation
  5. * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
  6. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #ifndef __FTPCI100_H
  23. #define __FTPCI100_H
  24. /* AHB Control Registers */
  25. struct ftpci100_ahbc {
  26. unsigned int iosize; /* 0x00 - I/O Space Size Signal */
  27. unsigned int prot; /* 0x04 - AHB Protection */
  28. unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
  29. unsigned int conf; /* 0x28 - PCI Configuration */
  30. unsigned int data; /* 0x2c - PCI Configuration DATA */
  31. };
  32. /*
  33. * FTPCI100_IOSIZE_REG's constant definitions
  34. */
  35. #define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
  36. /*
  37. * PCI Configuration Register
  38. */
  39. #define PCI_INT_MASK 0x4c
  40. #define PCI_MEM_BASE_SIZE1 0x50
  41. #define PCI_MEM_BASE_SIZE2 0x54
  42. #define PCI_MEM_BASE_SIZE3 0x58
  43. /*
  44. * PCI_INT_MASK's bit definitions
  45. */
  46. #define PCI_INTA_ENABLE (1 << 22)
  47. #define PCI_INTB_ENABLE (1 << 23)
  48. #define PCI_INTC_ENABLE (1 << 24)
  49. #define PCI_INTD_ENABLE (1 << 25)
  50. /*
  51. * PCI_MEM_BASE_SIZE1's constant definitions
  52. */
  53. #define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */
  54. #define FTPCI100_MAX_FUNCTIONS 20
  55. #define PCI_IRQ_LINES 4
  56. #define MAX_BUS_NUM 256
  57. #define MAX_DEV_NUM 32
  58. #define MAX_FUN_NUM 8
  59. #define PCI_MAX_BAR_PER_FUNC 6
  60. /*
  61. * PCI_MEM_SIZE
  62. */
  63. #define FTPCI100_MEM_SIZE(x) (ffs(x) << 24)
  64. /* This definition is used by pci_ftpci_init() */
  65. #define FTPCI100_BRIDGE_VENDORID 0x159b
  66. #define FTPCI100_BRIDGE_DEVICEID 0x4321
  67. struct pcibar {
  68. unsigned int size;
  69. unsigned int addr;
  70. };
  71. struct pci_config {
  72. unsigned int bus;
  73. unsigned int dev; /* device */
  74. unsigned int func;
  75. unsigned int pin;
  76. unsigned short v_id; /* vendor id */
  77. unsigned short d_id; /* device id */
  78. struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
  79. };
  80. #endif