smc91111.c 33 KB

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  1. /*------------------------------------------------------------------------
  2. . smc91111.c
  3. . This is a driver for SMSC's 91C111 single-chip Ethernet device.
  4. .
  5. . (C) Copyright 2002
  6. . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. . Rolf Offermanns <rof@sysgo.de>
  8. .
  9. . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
  10. . Developed by Simple Network Magic Corporation (SNMC)
  11. . Copyright (C) 1996 by Erik Stahlman (ES)
  12. .
  13. * SPDX-License-Identifier: GPL-2.0+
  14. .
  15. . Information contained in this file was obtained from the LAN91C111
  16. . manual from SMC. To get a copy, if you really want one, you can find
  17. . information under www.smsc.com.
  18. .
  19. .
  20. . "Features" of the SMC chip:
  21. . Integrated PHY/MAC for 10/100BaseT Operation
  22. . Supports internal and external MII
  23. . Integrated 8K packet memory
  24. . EEPROM interface for configuration
  25. .
  26. . Arguments:
  27. . io = for the base address
  28. . irq = for the IRQ
  29. .
  30. . author:
  31. . Erik Stahlman ( erik@vt.edu )
  32. . Daris A Nevil ( dnevil@snmc.com )
  33. .
  34. .
  35. . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
  36. .
  37. . Sources:
  38. . o SMSC LAN91C111 databook (www.smsc.com)
  39. . o smc9194.c by Erik Stahlman
  40. . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
  41. .
  42. . History:
  43. . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
  44. . 10/17/01 Marco Hasewinkel Modify for DNP/1110
  45. . 07/25/01 Woojung Huh Modify for ADS Bitsy
  46. . 04/25/01 Daris A Nevil Initial public release through SMSC
  47. . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
  48. ----------------------------------------------------------------------------*/
  49. #include <common.h>
  50. #include <command.h>
  51. #include <config.h>
  52. #include <malloc.h>
  53. #include "smc91111.h"
  54. #include <net.h>
  55. /* Use power-down feature of the chip */
  56. #define POWER_DOWN 0
  57. #define NO_AUTOPROBE
  58. #define SMC_DEBUG 0
  59. #if SMC_DEBUG > 1
  60. static const char version[] =
  61. "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
  62. #endif
  63. /* Autonegotiation timeout in seconds */
  64. #ifndef CONFIG_SMC_AUTONEG_TIMEOUT
  65. #define CONFIG_SMC_AUTONEG_TIMEOUT 10
  66. #endif
  67. /*------------------------------------------------------------------------
  68. .
  69. . Configuration options, for the experienced user to change.
  70. .
  71. -------------------------------------------------------------------------*/
  72. /*
  73. . Wait time for memory to be free. This probably shouldn't be
  74. . tuned that much, as waiting for this means nothing else happens
  75. . in the system
  76. */
  77. #define MEMORY_WAIT_TIME 16
  78. #if (SMC_DEBUG > 2 )
  79. #define PRINTK3(args...) printf(args)
  80. #else
  81. #define PRINTK3(args...)
  82. #endif
  83. #if SMC_DEBUG > 1
  84. #define PRINTK2(args...) printf(args)
  85. #else
  86. #define PRINTK2(args...)
  87. #endif
  88. #ifdef SMC_DEBUG
  89. #define PRINTK(args...) printf(args)
  90. #else
  91. #define PRINTK(args...)
  92. #endif
  93. /*------------------------------------------------------------------------
  94. .
  95. . The internal workings of the driver. If you are changing anything
  96. . here with the SMC stuff, you should have the datasheet and know
  97. . what you are doing.
  98. .
  99. -------------------------------------------------------------------------*/
  100. /* Memory sizing constant */
  101. #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
  102. #ifndef CONFIG_SMC91111_BASE
  103. #error "SMC91111 Base address must be passed to initialization funciton"
  104. /* #define CONFIG_SMC91111_BASE 0x20000300 */
  105. #endif
  106. #define SMC_DEV_NAME "SMC91111"
  107. #define SMC_PHY_ADDR 0x0000
  108. #define SMC_ALLOC_MAX_TRY 5
  109. #define SMC_TX_TIMEOUT 30
  110. #define SMC_PHY_CLOCK_DELAY 1000
  111. #define ETH_ZLEN 60
  112. #ifdef CONFIG_SMC_USE_32_BIT
  113. #define USE_32_BIT 1
  114. #else
  115. #undef USE_32_BIT
  116. #endif
  117. #ifdef SHARED_RESOURCES
  118. extern void swap_to(int device_id);
  119. #else
  120. # define swap_to(x)
  121. #endif
  122. #ifndef CONFIG_SMC91111_EXT_PHY
  123. static void smc_phy_configure(struct eth_device *dev);
  124. #endif /* !CONFIG_SMC91111_EXT_PHY */
  125. /*
  126. ------------------------------------------------------------
  127. .
  128. . Internal routines
  129. .
  130. ------------------------------------------------------------
  131. */
  132. #ifdef CONFIG_SMC_USE_IOFUNCS
  133. /*
  134. * input and output functions
  135. *
  136. * Implemented due to inx,outx macros accessing the device improperly
  137. * and putting the device into an unkown state.
  138. *
  139. * For instance, on Sharp LPD7A400 SDK, affects were chip memory
  140. * could not be free'd (hence the alloc failures), duplicate packets,
  141. * packets being corrupt (shifted) on the wire, etc. Switching to the
  142. * inx,outx functions fixed this problem.
  143. */
  144. static inline word SMC_inw(struct eth_device *dev, dword offset)
  145. {
  146. word v;
  147. v = *((volatile word*)(dev->iobase + offset));
  148. barrier(); *(volatile u32*)(0xc0000000);
  149. return v;
  150. }
  151. static inline void SMC_outw(struct eth_device *dev, word value, dword offset)
  152. {
  153. *((volatile word*)(dev->iobase + offset)) = value;
  154. barrier(); *(volatile u32*)(0xc0000000);
  155. }
  156. static inline byte SMC_inb(struct eth_device *dev, dword offset)
  157. {
  158. word _w;
  159. _w = SMC_inw(dev, offset & ~((dword)1));
  160. return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
  161. }
  162. static inline void SMC_outb(struct eth_device *dev, byte value, dword offset)
  163. {
  164. word _w;
  165. _w = SMC_inw(dev, offset & ~((dword)1));
  166. if (offset & 1)
  167. *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) =
  168. (value<<8) | (_w & 0x00ff);
  169. else
  170. *((volatile word*)(dev->iobase + offset)) =
  171. value | (_w & 0xff00);
  172. }
  173. static inline void SMC_insw(struct eth_device *dev, dword offset,
  174. volatile uchar* buf, dword len)
  175. {
  176. volatile word *p = (volatile word *)buf;
  177. while (len-- > 0) {
  178. *p++ = SMC_inw(dev, offset);
  179. barrier();
  180. *((volatile u32*)(0xc0000000));
  181. }
  182. }
  183. static inline void SMC_outsw(struct eth_device *dev, dword offset,
  184. uchar* buf, dword len)
  185. {
  186. volatile word *p = (volatile word *)buf;
  187. while (len-- > 0) {
  188. SMC_outw(dev, *p++, offset);
  189. barrier();
  190. *(volatile u32*)(0xc0000000);
  191. }
  192. }
  193. #endif /* CONFIG_SMC_USE_IOFUNCS */
  194. /*
  195. . A rather simple routine to print out a packet for debugging purposes.
  196. */
  197. #if SMC_DEBUG > 2
  198. static void print_packet( byte *, int );
  199. #endif
  200. #define tx_done(dev) 1
  201. static int poll4int (struct eth_device *dev, byte mask, int timeout)
  202. {
  203. int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
  204. int is_timeout = 0;
  205. word old_bank = SMC_inw (dev, BSR_REG);
  206. PRINTK2 ("Polling...\n");
  207. SMC_SELECT_BANK (dev, 2);
  208. while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
  209. if (get_timer (0) >= tmo) {
  210. is_timeout = 1;
  211. break;
  212. }
  213. }
  214. /* restore old bank selection */
  215. SMC_SELECT_BANK (dev, old_bank);
  216. if (is_timeout)
  217. return 1;
  218. else
  219. return 0;
  220. }
  221. /* Only one release command at a time, please */
  222. static inline void smc_wait_mmu_release_complete (struct eth_device *dev)
  223. {
  224. int count = 0;
  225. /* assume bank 2 selected */
  226. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  227. udelay (1); /* Wait until not busy */
  228. if (++count > 200)
  229. break;
  230. }
  231. }
  232. /*
  233. . Function: smc_reset( void )
  234. . Purpose:
  235. . This sets the SMC91111 chip to its normal state, hopefully from whatever
  236. . mess that any other DOS driver has put it in.
  237. .
  238. . Maybe I should reset more registers to defaults in here? SOFTRST should
  239. . do that for me.
  240. .
  241. . Method:
  242. . 1. send a SOFT RESET
  243. . 2. wait for it to finish
  244. . 3. enable autorelease mode
  245. . 4. reset the memory management unit
  246. . 5. clear all interrupts
  247. .
  248. */
  249. static void smc_reset (struct eth_device *dev)
  250. {
  251. PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
  252. /* This resets the registers mostly to defaults, but doesn't
  253. affect EEPROM. That seems unnecessary */
  254. SMC_SELECT_BANK (dev, 0);
  255. SMC_outw (dev, RCR_SOFTRST, RCR_REG);
  256. /* Setup the Configuration Register */
  257. /* This is necessary because the CONFIG_REG is not affected */
  258. /* by a soft reset */
  259. SMC_SELECT_BANK (dev, 1);
  260. #if defined(CONFIG_SMC91111_EXT_PHY)
  261. SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
  262. #else
  263. SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
  264. #endif
  265. /* Release from possible power-down state */
  266. /* Configuration register is not affected by Soft Reset */
  267. SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
  268. CONFIG_REG);
  269. SMC_SELECT_BANK (dev, 0);
  270. /* this should pause enough for the chip to be happy */
  271. udelay (10);
  272. /* Disable transmit and receive functionality */
  273. SMC_outw (dev, RCR_CLEAR, RCR_REG);
  274. SMC_outw (dev, TCR_CLEAR, TCR_REG);
  275. /* set the control register */
  276. SMC_SELECT_BANK (dev, 1);
  277. SMC_outw (dev, CTL_DEFAULT, CTL_REG);
  278. /* Reset the MMU */
  279. SMC_SELECT_BANK (dev, 2);
  280. smc_wait_mmu_release_complete (dev);
  281. SMC_outw (dev, MC_RESET, MMU_CMD_REG);
  282. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
  283. udelay (1); /* Wait until not busy */
  284. /* Note: It doesn't seem that waiting for the MMU busy is needed here,
  285. but this is a place where future chipsets _COULD_ break. Be wary
  286. of issuing another MMU command right after this */
  287. /* Disable all interrupts */
  288. SMC_outb (dev, 0, IM_REG);
  289. }
  290. /*
  291. . Function: smc_enable
  292. . Purpose: let the chip talk to the outside work
  293. . Method:
  294. . 1. Enable the transmitter
  295. . 2. Enable the receiver
  296. . 3. Enable interrupts
  297. */
  298. static void smc_enable(struct eth_device *dev)
  299. {
  300. PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
  301. SMC_SELECT_BANK( dev, 0 );
  302. /* see the header file for options in TCR/RCR DEFAULT*/
  303. SMC_outw( dev, TCR_DEFAULT, TCR_REG );
  304. SMC_outw( dev, RCR_DEFAULT, RCR_REG );
  305. /* clear MII_DIS */
  306. /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
  307. }
  308. /*
  309. . Function: smc_halt
  310. . Purpose: closes down the SMC91xxx chip.
  311. . Method:
  312. . 1. zero the interrupt mask
  313. . 2. clear the enable receive flag
  314. . 3. clear the enable xmit flags
  315. .
  316. . TODO:
  317. . (1) maybe utilize power down mode.
  318. . Why not yet? Because while the chip will go into power down mode,
  319. . the manual says that it will wake up in response to any I/O requests
  320. . in the register space. Empirical results do not show this working.
  321. */
  322. static void smc_halt(struct eth_device *dev)
  323. {
  324. PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
  325. /* no more interrupts for me */
  326. SMC_SELECT_BANK( dev, 2 );
  327. SMC_outb( dev, 0, IM_REG );
  328. /* and tell the card to stay away from that nasty outside world */
  329. SMC_SELECT_BANK( dev, 0 );
  330. SMC_outb( dev, RCR_CLEAR, RCR_REG );
  331. SMC_outb( dev, TCR_CLEAR, TCR_REG );
  332. swap_to(FLASH);
  333. }
  334. /*
  335. . Function: smc_send(struct net_device * )
  336. . Purpose:
  337. . This sends the actual packet to the SMC9xxx chip.
  338. .
  339. . Algorithm:
  340. . First, see if a saved_skb is available.
  341. . ( this should NOT be called if there is no 'saved_skb'
  342. . Now, find the packet number that the chip allocated
  343. . Point the data pointers at it in memory
  344. . Set the length word in the chip's memory
  345. . Dump the packet to chip memory
  346. . Check if a last byte is needed ( odd length packet )
  347. . if so, set the control flag right
  348. . Tell the card to send it
  349. . Enable the transmit interrupt, so I know if it failed
  350. . Free the kernel data if I actually sent it.
  351. */
  352. static int smc_send(struct eth_device *dev, void *packet, int packet_length)
  353. {
  354. byte packet_no;
  355. byte *buf;
  356. int length;
  357. int numPages;
  358. int try = 0;
  359. int time_out;
  360. byte status;
  361. byte saved_pnr;
  362. word saved_ptr;
  363. /* save PTR and PNR registers before manipulation */
  364. SMC_SELECT_BANK (dev, 2);
  365. saved_pnr = SMC_inb( dev, PN_REG );
  366. saved_ptr = SMC_inw( dev, PTR_REG );
  367. PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
  368. length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
  369. /* allocate memory
  370. ** The MMU wants the number of pages to be the number of 256 bytes
  371. ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
  372. **
  373. ** The 91C111 ignores the size bits, but the code is left intact
  374. ** for backwards and future compatibility.
  375. **
  376. ** Pkt size for allocating is data length +6 (for additional status
  377. ** words, length and ctl!)
  378. **
  379. ** If odd size then last byte is included in this header.
  380. */
  381. numPages = ((length & 0xfffe) + 6);
  382. numPages >>= 8; /* Divide by 256 */
  383. if (numPages > 7) {
  384. printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
  385. return 0;
  386. }
  387. /* now, try to allocate the memory */
  388. SMC_SELECT_BANK (dev, 2);
  389. SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
  390. /* FIXME: the ALLOC_INT bit never gets set *
  391. * so the following will always give a *
  392. * memory allocation error. *
  393. * same code works in armboot though *
  394. * -ro
  395. */
  396. again:
  397. try++;
  398. time_out = MEMORY_WAIT_TIME;
  399. do {
  400. status = SMC_inb (dev, SMC91111_INT_REG);
  401. if (status & IM_ALLOC_INT) {
  402. /* acknowledge the interrupt */
  403. SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
  404. break;
  405. }
  406. } while (--time_out);
  407. if (!time_out) {
  408. PRINTK2 ("%s: memory allocation, try %d failed ...\n",
  409. SMC_DEV_NAME, try);
  410. if (try < SMC_ALLOC_MAX_TRY)
  411. goto again;
  412. else
  413. return 0;
  414. }
  415. PRINTK2 ("%s: memory allocation, try %d succeeded ...\n",
  416. SMC_DEV_NAME, try);
  417. buf = (byte *) packet;
  418. /* If I get here, I _know_ there is a packet slot waiting for me */
  419. packet_no = SMC_inb (dev, AR_REG);
  420. if (packet_no & AR_FAILED) {
  421. /* or isn't there? BAD CHIP! */
  422. printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME);
  423. return 0;
  424. }
  425. /* we have a packet address, so tell the card to use it */
  426. #ifndef CONFIG_XAENIAX
  427. SMC_outb (dev, packet_no, PN_REG);
  428. #else
  429. /* On Xaeniax board, we can't use SMC_outb here because that way
  430. * the Allocate MMU command will end up written to the command register
  431. * as well, which will lead to a problem.
  432. */
  433. SMC_outl (dev, packet_no << 16, 0);
  434. #endif
  435. /* do not write new ptr value if Write data fifo not empty */
  436. while ( saved_ptr & PTR_NOTEMPTY )
  437. printf ("Write data fifo not empty!\n");
  438. /* point to the beginning of the packet */
  439. SMC_outw (dev, PTR_AUTOINC, PTR_REG);
  440. PRINTK3 ("%s: Trying to xmit packet of length %x\n",
  441. SMC_DEV_NAME, length);
  442. #if SMC_DEBUG > 2
  443. printf ("Transmitting Packet\n");
  444. print_packet (buf, length);
  445. #endif
  446. /* send the packet length ( +6 for status, length and ctl byte )
  447. and the status word ( set to zeros ) */
  448. #ifdef USE_32_BIT
  449. SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG);
  450. #else
  451. SMC_outw (dev, 0, SMC91111_DATA_REG);
  452. /* send the packet length ( +6 for status words, length, and ctl */
  453. SMC_outw (dev, (length + 6), SMC91111_DATA_REG);
  454. #endif
  455. /* send the actual data
  456. . I _think_ it's faster to send the longs first, and then
  457. . mop up by sending the last word. It depends heavily
  458. . on alignment, at least on the 486. Maybe it would be
  459. . a good idea to check which is optimal? But that could take
  460. . almost as much time as is saved?
  461. */
  462. #ifdef USE_32_BIT
  463. SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2);
  464. #ifndef CONFIG_XAENIAX
  465. if (length & 0x2)
  466. SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))),
  467. SMC91111_DATA_REG);
  468. #else
  469. /* On XANEIAX, we can only use 32-bit writes, so we need to handle
  470. * unaligned tail part specially. The standard code doesn't work.
  471. */
  472. if ((length & 3) == 3) {
  473. u16 * ptr = (u16*) &buf[length-3];
  474. SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16),
  475. SMC91111_DATA_REG);
  476. } else if ((length & 2) == 2) {
  477. u16 * ptr = (u16*) &buf[length-2];
  478. SMC_outl(dev, *ptr, SMC91111_DATA_REG);
  479. } else if (length & 1) {
  480. SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG);
  481. } else {
  482. SMC_outl(dev, 0, SMC91111_DATA_REG);
  483. }
  484. #endif
  485. #else
  486. SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1);
  487. #endif /* USE_32_BIT */
  488. #ifndef CONFIG_XAENIAX
  489. /* Send the last byte, if there is one. */
  490. if ((length & 1) == 0) {
  491. SMC_outw (dev, 0, SMC91111_DATA_REG);
  492. } else {
  493. SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG);
  494. }
  495. #endif
  496. /* and let the chipset deal with it */
  497. SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG);
  498. /* poll for TX INT */
  499. /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */
  500. /* poll for TX_EMPTY INT - autorelease enabled */
  501. if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) {
  502. /* sending failed */
  503. PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME);
  504. /* release packet */
  505. /* no need to release, MMU does that now */
  506. #ifdef CONFIG_XAENIAX
  507. SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
  508. #endif
  509. /* wait for MMU getting ready (low) */
  510. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  511. udelay (10);
  512. }
  513. PRINTK2 ("MMU ready\n");
  514. return 0;
  515. } else {
  516. /* ack. int */
  517. SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG);
  518. /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */
  519. PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME,
  520. length);
  521. /* release packet */
  522. /* no need to release, MMU does that now */
  523. #ifdef CONFIG_XAENIAX
  524. SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG);
  525. #endif
  526. /* wait for MMU getting ready (low) */
  527. while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) {
  528. udelay (10);
  529. }
  530. PRINTK2 ("MMU ready\n");
  531. }
  532. /* restore previously saved registers */
  533. #ifndef CONFIG_XAENIAX
  534. SMC_outb( dev, saved_pnr, PN_REG );
  535. #else
  536. /* On Xaeniax board, we can't use SMC_outb here because that way
  537. * the Allocate MMU command will end up written to the command register
  538. * as well, which will lead to a problem.
  539. */
  540. SMC_outl(dev, saved_pnr << 16, 0);
  541. #endif
  542. SMC_outw( dev, saved_ptr, PTR_REG );
  543. return length;
  544. }
  545. static int smc_write_hwaddr(struct eth_device *dev)
  546. {
  547. int i;
  548. swap_to(ETHERNET);
  549. SMC_SELECT_BANK (dev, 1);
  550. #ifdef USE_32_BIT
  551. for (i = 0; i < 6; i += 2) {
  552. word address;
  553. address = dev->enetaddr[i + 1] << 8;
  554. address |= dev->enetaddr[i];
  555. SMC_outw(dev, address, (ADDR0_REG + i));
  556. }
  557. #else
  558. for (i = 0; i < 6; i++)
  559. SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i));
  560. #endif
  561. swap_to(FLASH);
  562. return 0;
  563. }
  564. /*
  565. * Open and Initialize the board
  566. *
  567. * Set up everything, reset the card, etc ..
  568. *
  569. */
  570. static int smc_init(struct eth_device *dev, bd_t *bd)
  571. {
  572. swap_to(ETHERNET);
  573. PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME);
  574. /* reset the hardware */
  575. smc_reset (dev);
  576. smc_enable (dev);
  577. /* Configure the PHY */
  578. #ifndef CONFIG_SMC91111_EXT_PHY
  579. smc_phy_configure (dev);
  580. #endif
  581. /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
  582. /* SMC_SELECT_BANK(dev, 0); */
  583. /* SMC_outw(dev, 0, RPC_REG); */
  584. printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr);
  585. return 0;
  586. }
  587. /*-------------------------------------------------------------
  588. .
  589. . smc_rcv - receive a packet from the card
  590. .
  591. . There is ( at least ) a packet waiting to be read from
  592. . chip-memory.
  593. .
  594. . o Read the status
  595. . o If an error, record it
  596. . o otherwise, read in the packet
  597. --------------------------------------------------------------
  598. */
  599. static int smc_rcv(struct eth_device *dev)
  600. {
  601. int packet_number;
  602. word status;
  603. word packet_length;
  604. int is_error = 0;
  605. #ifdef USE_32_BIT
  606. dword stat_len;
  607. #endif
  608. byte saved_pnr;
  609. word saved_ptr;
  610. SMC_SELECT_BANK(dev, 2);
  611. /* save PTR and PTR registers */
  612. saved_pnr = SMC_inb( dev, PN_REG );
  613. saved_ptr = SMC_inw( dev, PTR_REG );
  614. packet_number = SMC_inw( dev, RXFIFO_REG );
  615. if ( packet_number & RXFIFO_REMPTY ) {
  616. return 0;
  617. }
  618. PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME);
  619. /* start reading from the start of the packet */
  620. SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
  621. /* First two words are status and packet_length */
  622. #ifdef USE_32_BIT
  623. stat_len = SMC_inl(dev, SMC91111_DATA_REG);
  624. status = stat_len & 0xffff;
  625. packet_length = stat_len >> 16;
  626. #else
  627. status = SMC_inw( dev, SMC91111_DATA_REG );
  628. packet_length = SMC_inw( dev, SMC91111_DATA_REG );
  629. #endif
  630. packet_length &= 0x07ff; /* mask off top bits */
  631. PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
  632. if ( !(status & RS_ERRORS ) ){
  633. /* Adjust for having already read the first two words */
  634. packet_length -= 4; /*4; */
  635. /* set odd length for bug in LAN91C111, */
  636. /* which never sets RS_ODDFRAME */
  637. /* TODO ? */
  638. #ifdef USE_32_BIT
  639. PRINTK3(" Reading %d dwords (and %d bytes)\n",
  640. packet_length >> 2, packet_length & 3 );
  641. /* QUESTION: Like in the TX routine, do I want
  642. to send the DWORDs or the bytes first, or some
  643. mixture. A mixture might improve already slow PIO
  644. performance */
  645. SMC_insl(dev, SMC91111_DATA_REG, net_rx_packets[0],
  646. packet_length >> 2);
  647. /* read the left over bytes */
  648. if (packet_length & 3) {
  649. int i;
  650. byte *tail = (byte *)(net_rx_packets[0] +
  651. (packet_length & ~3));
  652. dword leftover = SMC_inl(dev, SMC91111_DATA_REG);
  653. for (i=0; i<(packet_length & 3); i++)
  654. *tail++ = (byte) (leftover >> (8*i)) & 0xff;
  655. }
  656. #else
  657. PRINTK3(" Reading %d words and %d byte(s)\n",
  658. (packet_length >> 1 ), packet_length & 1 );
  659. SMC_insw(dev, SMC91111_DATA_REG , net_rx_packets[0],
  660. packet_length >> 1);
  661. #endif /* USE_32_BIT */
  662. #if SMC_DEBUG > 2
  663. printf("Receiving Packet\n");
  664. print_packet(net_rx_packets[0], packet_length);
  665. #endif
  666. } else {
  667. /* error ... */
  668. /* TODO ? */
  669. is_error = 1;
  670. }
  671. while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
  672. udelay(1); /* Wait until not busy */
  673. /* error or good, tell the card to get rid of this packet */
  674. SMC_outw( dev, MC_RELEASE, MMU_CMD_REG );
  675. while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY )
  676. udelay(1); /* Wait until not busy */
  677. /* restore saved registers */
  678. #ifndef CONFIG_XAENIAX
  679. SMC_outb( dev, saved_pnr, PN_REG );
  680. #else
  681. /* On Xaeniax board, we can't use SMC_outb here because that way
  682. * the Allocate MMU command will end up written to the command register
  683. * as well, which will lead to a problem.
  684. */
  685. SMC_outl( dev, saved_pnr << 16, 0);
  686. #endif
  687. SMC_outw( dev, saved_ptr, PTR_REG );
  688. if (!is_error) {
  689. /* Pass the packet up to the protocol layers. */
  690. net_process_received_packet(net_rx_packets[0], packet_length);
  691. return packet_length;
  692. } else {
  693. return 0;
  694. }
  695. }
  696. #if 0
  697. /*------------------------------------------------------------
  698. . Modify a bit in the LAN91C111 register set
  699. .-------------------------------------------------------------*/
  700. static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg,
  701. unsigned int bit, int val)
  702. {
  703. word regval;
  704. SMC_SELECT_BANK( dev, bank );
  705. regval = SMC_inw( dev, reg );
  706. if (val)
  707. regval |= bit;
  708. else
  709. regval &= ~bit;
  710. SMC_outw( dev, regval, 0 );
  711. return(regval);
  712. }
  713. /*------------------------------------------------------------
  714. . Retrieve a bit in the LAN91C111 register set
  715. .-------------------------------------------------------------*/
  716. static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit)
  717. {
  718. SMC_SELECT_BANK( dev, bank );
  719. if ( SMC_inw( dev, reg ) & bit)
  720. return(1);
  721. else
  722. return(0);
  723. }
  724. /*------------------------------------------------------------
  725. . Modify a LAN91C111 register (word access only)
  726. .-------------------------------------------------------------*/
  727. static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val)
  728. {
  729. SMC_SELECT_BANK( dev, bank );
  730. SMC_outw( dev, val, reg );
  731. }
  732. /*------------------------------------------------------------
  733. . Retrieve a LAN91C111 register (word access only)
  734. .-------------------------------------------------------------*/
  735. static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg)
  736. {
  737. SMC_SELECT_BANK( dev, bank );
  738. return(SMC_inw( dev, reg ));
  739. }
  740. #endif /* 0 */
  741. /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
  742. #if (SMC_DEBUG > 2 )
  743. /*------------------------------------------------------------
  744. . Debugging function for viewing MII Management serial bitstream
  745. .-------------------------------------------------------------*/
  746. static void smc_dump_mii_stream (byte * bits, int size)
  747. {
  748. int i;
  749. printf ("BIT#:");
  750. for (i = 0; i < size; ++i) {
  751. printf ("%d", i % 10);
  752. }
  753. printf ("\nMDOE:");
  754. for (i = 0; i < size; ++i) {
  755. if (bits[i] & MII_MDOE)
  756. printf ("1");
  757. else
  758. printf ("0");
  759. }
  760. printf ("\nMDO :");
  761. for (i = 0; i < size; ++i) {
  762. if (bits[i] & MII_MDO)
  763. printf ("1");
  764. else
  765. printf ("0");
  766. }
  767. printf ("\nMDI :");
  768. for (i = 0; i < size; ++i) {
  769. if (bits[i] & MII_MDI)
  770. printf ("1");
  771. else
  772. printf ("0");
  773. }
  774. printf ("\n");
  775. }
  776. #endif
  777. /*------------------------------------------------------------
  778. . Reads a register from the MII Management serial interface
  779. .-------------------------------------------------------------*/
  780. #ifndef CONFIG_SMC91111_EXT_PHY
  781. static word smc_read_phy_register (struct eth_device *dev, byte phyreg)
  782. {
  783. int oldBank;
  784. int i;
  785. byte mask;
  786. word mii_reg;
  787. byte bits[64];
  788. int clk_idx = 0;
  789. int input_idx;
  790. word phydata;
  791. byte phyaddr = SMC_PHY_ADDR;
  792. /* 32 consecutive ones on MDO to establish sync */
  793. for (i = 0; i < 32; ++i)
  794. bits[clk_idx++] = MII_MDOE | MII_MDO;
  795. /* Start code <01> */
  796. bits[clk_idx++] = MII_MDOE;
  797. bits[clk_idx++] = MII_MDOE | MII_MDO;
  798. /* Read command <10> */
  799. bits[clk_idx++] = MII_MDOE | MII_MDO;
  800. bits[clk_idx++] = MII_MDOE;
  801. /* Output the PHY address, msb first */
  802. mask = (byte) 0x10;
  803. for (i = 0; i < 5; ++i) {
  804. if (phyaddr & mask)
  805. bits[clk_idx++] = MII_MDOE | MII_MDO;
  806. else
  807. bits[clk_idx++] = MII_MDOE;
  808. /* Shift to next lowest bit */
  809. mask >>= 1;
  810. }
  811. /* Output the phy register number, msb first */
  812. mask = (byte) 0x10;
  813. for (i = 0; i < 5; ++i) {
  814. if (phyreg & mask)
  815. bits[clk_idx++] = MII_MDOE | MII_MDO;
  816. else
  817. bits[clk_idx++] = MII_MDOE;
  818. /* Shift to next lowest bit */
  819. mask >>= 1;
  820. }
  821. /* Tristate and turnaround (2 bit times) */
  822. bits[clk_idx++] = 0;
  823. /*bits[clk_idx++] = 0; */
  824. /* Input starts at this bit time */
  825. input_idx = clk_idx;
  826. /* Will input 16 bits */
  827. for (i = 0; i < 16; ++i)
  828. bits[clk_idx++] = 0;
  829. /* Final clock bit */
  830. bits[clk_idx++] = 0;
  831. /* Save the current bank */
  832. oldBank = SMC_inw (dev, BANK_SELECT);
  833. /* Select bank 3 */
  834. SMC_SELECT_BANK (dev, 3);
  835. /* Get the current MII register value */
  836. mii_reg = SMC_inw (dev, MII_REG);
  837. /* Turn off all MII Interface bits */
  838. mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  839. /* Clock all 64 cycles */
  840. for (i = 0; i < sizeof bits; ++i) {
  841. /* Clock Low - output data */
  842. SMC_outw (dev, mii_reg | bits[i], MII_REG);
  843. udelay (SMC_PHY_CLOCK_DELAY);
  844. /* Clock Hi - input data */
  845. SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
  846. udelay (SMC_PHY_CLOCK_DELAY);
  847. bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
  848. }
  849. /* Return to idle state */
  850. /* Set clock to low, data to low, and output tristated */
  851. SMC_outw (dev, mii_reg, MII_REG);
  852. udelay (SMC_PHY_CLOCK_DELAY);
  853. /* Restore original bank select */
  854. SMC_SELECT_BANK (dev, oldBank);
  855. /* Recover input data */
  856. phydata = 0;
  857. for (i = 0; i < 16; ++i) {
  858. phydata <<= 1;
  859. if (bits[input_idx++] & MII_MDI)
  860. phydata |= 0x0001;
  861. }
  862. #if (SMC_DEBUG > 2 )
  863. printf ("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
  864. phyaddr, phyreg, phydata);
  865. smc_dump_mii_stream (bits, sizeof bits);
  866. #endif
  867. return (phydata);
  868. }
  869. /*------------------------------------------------------------
  870. . Writes a register to the MII Management serial interface
  871. .-------------------------------------------------------------*/
  872. static void smc_write_phy_register (struct eth_device *dev, byte phyreg,
  873. word phydata)
  874. {
  875. int oldBank;
  876. int i;
  877. word mask;
  878. word mii_reg;
  879. byte bits[65];
  880. int clk_idx = 0;
  881. byte phyaddr = SMC_PHY_ADDR;
  882. /* 32 consecutive ones on MDO to establish sync */
  883. for (i = 0; i < 32; ++i)
  884. bits[clk_idx++] = MII_MDOE | MII_MDO;
  885. /* Start code <01> */
  886. bits[clk_idx++] = MII_MDOE;
  887. bits[clk_idx++] = MII_MDOE | MII_MDO;
  888. /* Write command <01> */
  889. bits[clk_idx++] = MII_MDOE;
  890. bits[clk_idx++] = MII_MDOE | MII_MDO;
  891. /* Output the PHY address, msb first */
  892. mask = (byte) 0x10;
  893. for (i = 0; i < 5; ++i) {
  894. if (phyaddr & mask)
  895. bits[clk_idx++] = MII_MDOE | MII_MDO;
  896. else
  897. bits[clk_idx++] = MII_MDOE;
  898. /* Shift to next lowest bit */
  899. mask >>= 1;
  900. }
  901. /* Output the phy register number, msb first */
  902. mask = (byte) 0x10;
  903. for (i = 0; i < 5; ++i) {
  904. if (phyreg & mask)
  905. bits[clk_idx++] = MII_MDOE | MII_MDO;
  906. else
  907. bits[clk_idx++] = MII_MDOE;
  908. /* Shift to next lowest bit */
  909. mask >>= 1;
  910. }
  911. /* Tristate and turnaround (2 bit times) */
  912. bits[clk_idx++] = 0;
  913. bits[clk_idx++] = 0;
  914. /* Write out 16 bits of data, msb first */
  915. mask = 0x8000;
  916. for (i = 0; i < 16; ++i) {
  917. if (phydata & mask)
  918. bits[clk_idx++] = MII_MDOE | MII_MDO;
  919. else
  920. bits[clk_idx++] = MII_MDOE;
  921. /* Shift to next lowest bit */
  922. mask >>= 1;
  923. }
  924. /* Final clock bit (tristate) */
  925. bits[clk_idx++] = 0;
  926. /* Save the current bank */
  927. oldBank = SMC_inw (dev, BANK_SELECT);
  928. /* Select bank 3 */
  929. SMC_SELECT_BANK (dev, 3);
  930. /* Get the current MII register value */
  931. mii_reg = SMC_inw (dev, MII_REG);
  932. /* Turn off all MII Interface bits */
  933. mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO);
  934. /* Clock all cycles */
  935. for (i = 0; i < sizeof bits; ++i) {
  936. /* Clock Low - output data */
  937. SMC_outw (dev, mii_reg | bits[i], MII_REG);
  938. udelay (SMC_PHY_CLOCK_DELAY);
  939. /* Clock Hi - input data */
  940. SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG);
  941. udelay (SMC_PHY_CLOCK_DELAY);
  942. bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI;
  943. }
  944. /* Return to idle state */
  945. /* Set clock to low, data to low, and output tristated */
  946. SMC_outw (dev, mii_reg, MII_REG);
  947. udelay (SMC_PHY_CLOCK_DELAY);
  948. /* Restore original bank select */
  949. SMC_SELECT_BANK (dev, oldBank);
  950. #if (SMC_DEBUG > 2 )
  951. printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
  952. phyaddr, phyreg, phydata);
  953. smc_dump_mii_stream (bits, sizeof bits);
  954. #endif
  955. }
  956. #endif /* !CONFIG_SMC91111_EXT_PHY */
  957. /*------------------------------------------------------------
  958. . Configures the specified PHY using Autonegotiation. Calls
  959. . smc_phy_fixed() if the user has requested a certain config.
  960. .-------------------------------------------------------------*/
  961. #ifndef CONFIG_SMC91111_EXT_PHY
  962. static void smc_phy_configure (struct eth_device *dev)
  963. {
  964. int timeout;
  965. word my_phy_caps; /* My PHY capabilities */
  966. word my_ad_caps; /* My Advertised capabilities */
  967. word status = 0; /*;my status = 0 */
  968. PRINTK3 ("%s: smc_program_phy()\n", SMC_DEV_NAME);
  969. /* Reset the PHY, setting all other bits to zero */
  970. smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST);
  971. /* Wait for the reset to complete, or time out */
  972. timeout = 6; /* Wait up to 3 seconds */
  973. while (timeout--) {
  974. if (!(smc_read_phy_register (dev, PHY_CNTL_REG)
  975. & PHY_CNTL_RST)) {
  976. /* reset complete */
  977. break;
  978. }
  979. mdelay(500); /* wait 500 millisecs */
  980. }
  981. if (timeout < 1) {
  982. printf ("%s:PHY reset timed out\n", SMC_DEV_NAME);
  983. goto smc_phy_configure_exit;
  984. }
  985. /* Read PHY Register 18, Status Output */
  986. /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
  987. /* Enable PHY Interrupts (for register 18) */
  988. /* Interrupts listed here are disabled */
  989. smc_write_phy_register (dev, PHY_MASK_REG, 0xffff);
  990. /* Configure the Receive/Phy Control register */
  991. SMC_SELECT_BANK (dev, 0);
  992. SMC_outw (dev, RPC_DEFAULT, RPC_REG);
  993. /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
  994. my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG);
  995. my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
  996. if (my_phy_caps & PHY_STAT_CAP_T4)
  997. my_ad_caps |= PHY_AD_T4;
  998. if (my_phy_caps & PHY_STAT_CAP_TXF)
  999. my_ad_caps |= PHY_AD_TX_FDX;
  1000. if (my_phy_caps & PHY_STAT_CAP_TXH)
  1001. my_ad_caps |= PHY_AD_TX_HDX;
  1002. if (my_phy_caps & PHY_STAT_CAP_TF)
  1003. my_ad_caps |= PHY_AD_10_FDX;
  1004. if (my_phy_caps & PHY_STAT_CAP_TH)
  1005. my_ad_caps |= PHY_AD_10_HDX;
  1006. /* Update our Auto-Neg Advertisement Register */
  1007. smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps);
  1008. /* Read the register back. Without this, it appears that when */
  1009. /* auto-negotiation is restarted, sometimes it isn't ready and */
  1010. /* the link does not come up. */
  1011. smc_read_phy_register(dev, PHY_AD_REG);
  1012. PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
  1013. PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
  1014. /* Restart auto-negotiation process in order to advertise my caps */
  1015. smc_write_phy_register (dev, PHY_CNTL_REG,
  1016. PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST);
  1017. /* Wait for the auto-negotiation to complete. This may take from */
  1018. /* 2 to 3 seconds. */
  1019. /* Wait for the reset to complete, or time out */
  1020. timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2;
  1021. while (timeout--) {
  1022. status = smc_read_phy_register (dev, PHY_STAT_REG);
  1023. if (status & PHY_STAT_ANEG_ACK) {
  1024. /* auto-negotiate complete */
  1025. break;
  1026. }
  1027. mdelay(500); /* wait 500 millisecs */
  1028. /* Restart auto-negotiation if remote fault */
  1029. if (status & PHY_STAT_REM_FLT) {
  1030. printf ("%s: PHY remote fault detected\n",
  1031. SMC_DEV_NAME);
  1032. /* Restart auto-negotiation */
  1033. printf ("%s: PHY restarting auto-negotiation\n",
  1034. SMC_DEV_NAME);
  1035. smc_write_phy_register (dev, PHY_CNTL_REG,
  1036. PHY_CNTL_ANEG_EN |
  1037. PHY_CNTL_ANEG_RST |
  1038. PHY_CNTL_SPEED |
  1039. PHY_CNTL_DPLX);
  1040. }
  1041. }
  1042. if (timeout < 1) {
  1043. printf ("%s: PHY auto-negotiate timed out\n", SMC_DEV_NAME);
  1044. }
  1045. /* Fail if we detected an auto-negotiate remote fault */
  1046. if (status & PHY_STAT_REM_FLT) {
  1047. printf ("%s: PHY remote fault detected\n", SMC_DEV_NAME);
  1048. }
  1049. /* Re-Configure the Receive/Phy Control register */
  1050. SMC_outw (dev, RPC_DEFAULT, RPC_REG);
  1051. smc_phy_configure_exit: ;
  1052. }
  1053. #endif /* !CONFIG_SMC91111_EXT_PHY */
  1054. #if SMC_DEBUG > 2
  1055. static void print_packet( byte * buf, int length )
  1056. {
  1057. int i;
  1058. int remainder;
  1059. int lines;
  1060. printf("Packet of length %d \n", length );
  1061. #if SMC_DEBUG > 3
  1062. lines = length / 16;
  1063. remainder = length % 16;
  1064. for ( i = 0; i < lines ; i ++ ) {
  1065. int cur;
  1066. for ( cur = 0; cur < 8; cur ++ ) {
  1067. byte a, b;
  1068. a = *(buf ++ );
  1069. b = *(buf ++ );
  1070. printf("%02x%02x ", a, b );
  1071. }
  1072. printf("\n");
  1073. }
  1074. for ( i = 0; i < remainder/2 ; i++ ) {
  1075. byte a, b;
  1076. a = *(buf ++ );
  1077. b = *(buf ++ );
  1078. printf("%02x%02x ", a, b );
  1079. }
  1080. printf("\n");
  1081. #endif
  1082. }
  1083. #endif
  1084. int smc91111_initialize(u8 dev_num, int base_addr)
  1085. {
  1086. struct smc91111_priv *priv;
  1087. struct eth_device *dev;
  1088. int i;
  1089. priv = malloc(sizeof(*priv));
  1090. if (!priv)
  1091. return 0;
  1092. dev = malloc(sizeof(*dev));
  1093. if (!dev) {
  1094. free(priv);
  1095. return 0;
  1096. }
  1097. memset(dev, 0, sizeof(*dev));
  1098. priv->dev_num = dev_num;
  1099. dev->priv = priv;
  1100. dev->iobase = base_addr;
  1101. swap_to(ETHERNET);
  1102. SMC_SELECT_BANK(dev, 1);
  1103. for (i = 0; i < 6; ++i)
  1104. dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i));
  1105. swap_to(FLASH);
  1106. dev->init = smc_init;
  1107. dev->halt = smc_halt;
  1108. dev->send = smc_send;
  1109. dev->recv = smc_rcv;
  1110. dev->write_hwaddr = smc_write_hwaddr;
  1111. sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num);
  1112. eth_register(dev);
  1113. return 0;
  1114. }