aspeed-common.h 1.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071
  1. /*
  2. * Copyright (C) 2012-2020 ASPEED Technology Inc.
  3. * Ryan Chen <ryan_chen@aspeedtech.com>
  4. *
  5. * Copyright 2016 IBM Corporation
  6. * (C) Copyright 2016 Google, Inc
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #ifndef __AST_COMMON_CONFIG_H
  11. #define __AST_COMMON_CONFIG_H
  12. /* Misc CPU related */
  13. #define CONFIG_CMDLINE_TAG
  14. #define CONFIG_SETUP_MEMORY_TAGS
  15. #define CONFIG_INITRD_TAG
  16. #define CONFIG_CMDLINE_EDITING
  17. /* Enable cache controller */
  18. #define CONFIG_SYS_DCACHE_OFF
  19. #define CONFIG_SYS_SDRAM_BASE 0x80000000
  20. #ifdef CONFIG_PRE_CON_BUF_SZ
  21. #define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000 + CONFIG_PRE_CON_BUF_SZ)
  22. #define CONFIG_SYS_INIT_RAM_SIZE (36*1024 - CONFIG_PRE_CON_BUF_SZ)
  23. #else
  24. #define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000)
  25. #define CONFIG_SYS_INIT_RAM_SIZE (36*1024)
  26. #endif
  27. #define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
  28. + CONFIG_SYS_INIT_RAM_SIZE)
  29. #define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \
  30. - GENERATED_GBL_DATA_SIZE)
  31. #define CONFIG_NR_DRAM_BANKS 1
  32. #define CONFIG_SYS_MALLOC_LEN (32 << 20)
  33. /*
  34. * NS16550 Configuration
  35. */
  36. /*
  37. * BOOTP options
  38. */
  39. #define CONFIG_BOOTP_BOOTFILESIZE
  40. #define CONFIG_BOOTP_BOOTPATH
  41. #define CONFIG_BOOTP_GATEWAY
  42. #define CONFIG_BOOTP_HOSTNAME
  43. #define CONFIG_BOOTP_SUBNETMASK
  44. /*
  45. * Miscellaneous configurable options
  46. */
  47. #define CONFIG_SYS_LONGHELP
  48. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  49. #define CONFIG_BOOTCOMMAND "bootm 20080000 20300000"
  50. #define CONFIG_ENV_OVERWRITE
  51. #define CONFIG_EXTRA_ENV_SETTINGS \
  52. "verify=yes\0" \
  53. "spi_dma=yes\0" \
  54. ""
  55. #endif /* __AST_COMMON_CONFIG_H */