ddr.h 1.3 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __DDR_H__
  7. #define __DDR_H__
  8. struct board_specific_parameters {
  9. u32 n_ranks;
  10. u32 datarate_mhz_high;
  11. u32 rank_gb;
  12. u32 clk_adjust;
  13. u32 wrlvl_start;
  14. u32 wrlvl_ctl_2;
  15. u32 wrlvl_ctl_3;
  16. };
  17. /*
  18. * These tables contain all valid speeds we want to override with board
  19. * specific parameters. datarate_mhz_high values need to be in ascending order
  20. * for each n_ranks group.
  21. */
  22. static const struct board_specific_parameters udimm0[] = {
  23. /*
  24. * memory controller 0
  25. * num| hi| rank| clk| wrlvl | wrlvl
  26. * ranks| mhz| GB |adjst| start | ctl2
  27. */
  28. {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
  29. {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
  30. {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
  31. {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
  32. {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
  33. {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
  34. {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
  35. {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
  36. {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
  37. {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
  38. {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
  39. {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
  40. {}
  41. };
  42. static const struct board_specific_parameters *udimms[] = {
  43. udimm0,
  44. };
  45. #endif