cpu.c 872 B

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  1. /*
  2. * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <asm/arcregs.h>
  8. #include <asm/cache.h>
  9. DECLARE_GLOBAL_DATA_PTR;
  10. int arch_cpu_init(void)
  11. {
  12. #ifdef CONFIG_SYS_ICACHE_OFF
  13. icache_disable();
  14. #else
  15. icache_enable();
  16. invalidate_icache_all();
  17. #endif
  18. flush_dcache_all();
  19. #ifdef CONFIG_SYS_DCACHE_OFF
  20. dcache_disable();
  21. #else
  22. dcache_enable();
  23. #endif
  24. timer_init();
  25. /* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
  26. if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
  27. gd->arch.running_on_hw = 0;
  28. else
  29. gd->arch.running_on_hw = 1;
  30. gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
  31. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  32. return 0;
  33. }
  34. int arch_early_init_r(void)
  35. {
  36. gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
  37. gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
  38. return 0;
  39. }