config_mpc85xx.h 19 KB

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  1. /*
  2. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of
  7. * the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17. * MA 02111-1307 USA
  18. *
  19. */
  20. #ifndef _ASM_MPC85xx_CONFIG_H_
  21. #define _ASM_MPC85xx_CONFIG_H_
  22. /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
  23. #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
  24. #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
  25. #endif
  26. #define FSL_DDR_VER_4_7 47
  27. /* Number of TLB CAM entries we have on FSL Book-E chips */
  28. #if defined(CONFIG_E500MC)
  29. #define CONFIG_SYS_NUM_TLBCAMS 64
  30. #elif defined(CONFIG_E500)
  31. #define CONFIG_SYS_NUM_TLBCAMS 16
  32. #endif
  33. #if defined(CONFIG_MPC8536)
  34. #define CONFIG_MAX_CPUS 1
  35. #define CONFIG_SYS_FSL_NUM_LAWS 12
  36. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
  37. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  38. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  39. #elif defined(CONFIG_MPC8540)
  40. #define CONFIG_MAX_CPUS 1
  41. #define CONFIG_SYS_FSL_NUM_LAWS 8
  42. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  43. #elif defined(CONFIG_MPC8541)
  44. #define CONFIG_MAX_CPUS 1
  45. #define CONFIG_SYS_FSL_NUM_LAWS 8
  46. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  47. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  48. #elif defined(CONFIG_MPC8544)
  49. #define CONFIG_MAX_CPUS 1
  50. #define CONFIG_SYS_FSL_NUM_LAWS 10
  51. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
  52. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  53. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  54. #elif defined(CONFIG_MPC8548)
  55. #define CONFIG_MAX_CPUS 1
  56. #define CONFIG_SYS_FSL_NUM_LAWS 10
  57. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
  58. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  59. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  60. #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
  61. #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
  62. #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  63. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  64. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  65. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  66. #define CONFIG_SYS_FSL_RMU
  67. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  68. #elif defined(CONFIG_MPC8555)
  69. #define CONFIG_MAX_CPUS 1
  70. #define CONFIG_SYS_FSL_NUM_LAWS 8
  71. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  72. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  73. #elif defined(CONFIG_MPC8560)
  74. #define CONFIG_MAX_CPUS 1
  75. #define CONFIG_SYS_FSL_NUM_LAWS 8
  76. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  77. #elif defined(CONFIG_MPC8568)
  78. #define CONFIG_MAX_CPUS 1
  79. #define CONFIG_SYS_FSL_NUM_LAWS 10
  80. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  81. #define QE_MURAM_SIZE 0x10000UL
  82. #define MAX_QE_RISC 2
  83. #define QE_NUM_OF_SNUM 28
  84. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  85. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  86. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  87. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  88. #define CONFIG_SYS_FSL_RMU
  89. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  90. #elif defined(CONFIG_MPC8569)
  91. #define CONFIG_MAX_CPUS 1
  92. #define CONFIG_SYS_FSL_NUM_LAWS 10
  93. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  94. #define QE_MURAM_SIZE 0x20000UL
  95. #define MAX_QE_RISC 4
  96. #define QE_NUM_OF_SNUM 46
  97. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  98. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  99. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  100. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  101. #define CONFIG_SYS_FSL_RMU
  102. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  103. #elif defined(CONFIG_MPC8572)
  104. #define CONFIG_MAX_CPUS 2
  105. #define CONFIG_SYS_FSL_NUM_LAWS 12
  106. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  107. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  108. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  109. #define CONFIG_SYS_FSL_ERRATUM_DDR_115
  110. #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  111. #elif defined(CONFIG_P1010)
  112. #define CONFIG_MAX_CPUS 1
  113. #define CONFIG_FSL_SDHC_V2_3
  114. #define CONFIG_SYS_FSL_NUM_LAWS 12
  115. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  116. #define CONFIG_TSECV2
  117. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  118. #define CONFIG_FSL_SATA_V2
  119. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  120. #define CONFIG_NUM_DDR_CONTROLLERS 1
  121. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  122. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  123. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  124. #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
  125. #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  126. #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  127. /* P1011 is single core version of P1020 */
  128. #elif defined(CONFIG_P1011)
  129. #define CONFIG_MAX_CPUS 1
  130. #define CONFIG_SYS_FSL_NUM_LAWS 12
  131. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  132. #define CONFIG_TSECV2
  133. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  134. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  135. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  136. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  137. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  138. /* P1012 is single core version of P1021 */
  139. #elif defined(CONFIG_P1012)
  140. #define CONFIG_MAX_CPUS 1
  141. #define CONFIG_SYS_FSL_NUM_LAWS 12
  142. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  143. #define CONFIG_TSECV2
  144. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  145. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  146. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  147. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  148. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  149. #define QE_MURAM_SIZE 0x6000UL
  150. #define MAX_QE_RISC 1
  151. #define QE_NUM_OF_SNUM 28
  152. /* P1013 is single core version of P1022 */
  153. #elif defined(CONFIG_P1013)
  154. #define CONFIG_MAX_CPUS 1
  155. #define CONFIG_SYS_FSL_NUM_LAWS 12
  156. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  157. #define CONFIG_TSECV2
  158. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  159. #define CONFIG_FSL_SATA_V2
  160. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  161. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  162. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  163. #define CONFIG_FSL_SATA_ERRATUM_A001
  164. #elif defined(CONFIG_P1014)
  165. #define CONFIG_MAX_CPUS 1
  166. #define CONFIG_FSL_SDHC_V2_3
  167. #define CONFIG_SYS_FSL_NUM_LAWS 12
  168. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  169. #define CONFIG_TSECV2
  170. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  171. #define CONFIG_FSL_SATA_V2
  172. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  173. #define CONFIG_NUM_DDR_CONTROLLERS 1
  174. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  175. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  176. #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
  177. #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  178. #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  179. /* P1017 is single core version of P1023 */
  180. #elif defined(CONFIG_P1017)
  181. #define CONFIG_MAX_CPUS 1
  182. #define CONFIG_SYS_FSL_NUM_LAWS 12
  183. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  184. #define CONFIG_SYS_NUM_FMAN 1
  185. #define CONFIG_SYS_NUM_FM1_DTSEC 2
  186. #define CONFIG_NUM_DDR_CONTROLLERS 1
  187. #define CONFIG_SYS_QMAN_NUM_PORTALS 3
  188. #define CONFIG_SYS_BMAN_NUM_PORTALS 3
  189. #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
  190. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  191. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
  192. #elif defined(CONFIG_P1020)
  193. #define CONFIG_MAX_CPUS 2
  194. #define CONFIG_SYS_FSL_NUM_LAWS 12
  195. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  196. #define CONFIG_TSECV2
  197. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  198. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  199. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  200. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  201. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  202. #elif defined(CONFIG_P1021)
  203. #define CONFIG_MAX_CPUS 2
  204. #define CONFIG_SYS_FSL_NUM_LAWS 12
  205. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  206. #define CONFIG_TSECV2
  207. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  208. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  209. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  210. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  211. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  212. #define QE_MURAM_SIZE 0x6000UL
  213. #define MAX_QE_RISC 1
  214. #define QE_NUM_OF_SNUM 28
  215. #elif defined(CONFIG_P1022)
  216. #define CONFIG_MAX_CPUS 2
  217. #define CONFIG_SYS_FSL_NUM_LAWS 12
  218. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  219. #define CONFIG_TSECV2
  220. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  221. #define CONFIG_FSL_SATA_V2
  222. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  223. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  224. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  225. #define CONFIG_FSL_SATA_ERRATUM_A001
  226. #elif defined(CONFIG_P1023)
  227. #define CONFIG_MAX_CPUS 2
  228. #define CONFIG_SYS_FSL_NUM_LAWS 12
  229. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  230. #define CONFIG_SYS_NUM_FMAN 1
  231. #define CONFIG_SYS_NUM_FM1_DTSEC 2
  232. #define CONFIG_NUM_DDR_CONTROLLERS 1
  233. #define CONFIG_SYS_QMAN_NUM_PORTALS 3
  234. #define CONFIG_SYS_BMAN_NUM_PORTALS 3
  235. #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
  236. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  237. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
  238. /* P1024 is lower end variant of P1020 */
  239. #elif defined(CONFIG_P1024)
  240. #define CONFIG_MAX_CPUS 2
  241. #define CONFIG_SYS_FSL_NUM_LAWS 12
  242. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  243. #define CONFIG_TSECV2
  244. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  245. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  246. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  247. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  248. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  249. /* P1025 is lower end variant of P1021 */
  250. #elif defined(CONFIG_P1025)
  251. #define CONFIG_MAX_CPUS 2
  252. #define CONFIG_SYS_FSL_NUM_LAWS 12
  253. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  254. #define CONFIG_TSECV2
  255. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  256. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  257. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  258. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  259. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  260. #define QE_MURAM_SIZE 0x6000UL
  261. #define MAX_QE_RISC 1
  262. #define QE_NUM_OF_SNUM 28
  263. /* P2010 is single core version of P2020 */
  264. #elif defined(CONFIG_P2010)
  265. #define CONFIG_MAX_CPUS 1
  266. #define CONFIG_SYS_FSL_NUM_LAWS 12
  267. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  268. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  269. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  270. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  271. #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  272. #elif defined(CONFIG_P2020)
  273. #define CONFIG_MAX_CPUS 2
  274. #define CONFIG_SYS_FSL_NUM_LAWS 12
  275. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  276. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  277. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  278. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  279. #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  280. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  281. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  282. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  283. #define CONFIG_SYS_FSL_RMU
  284. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  285. #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
  286. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  287. #define CONFIG_MAX_CPUS 4
  288. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  289. #define CONFIG_SYS_FSL_NUM_LAWS 32
  290. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  291. #define CONFIG_FSL_SATA_V2
  292. #define CONFIG_SYS_NUM_FMAN 1
  293. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  294. #define CONFIG_SYS_NUM_FM1_10GEC 1
  295. #define CONFIG_NUM_DDR_CONTROLLERS 1
  296. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  297. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  298. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  299. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  300. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  301. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  302. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  303. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  304. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  305. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  306. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  307. #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
  308. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  309. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  310. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  311. #define CONFIG_SYS_FSL_ERRATUM_A004510
  312. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  313. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
  314. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  315. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  316. #elif defined(CONFIG_PPC_P3041)
  317. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  318. #define CONFIG_MAX_CPUS 4
  319. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  320. #define CONFIG_SYS_FSL_NUM_LAWS 32
  321. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  322. #define CONFIG_FSL_SATA_V2
  323. #define CONFIG_SYS_NUM_FMAN 1
  324. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  325. #define CONFIG_SYS_NUM_FM1_10GEC 1
  326. #define CONFIG_NUM_DDR_CONTROLLERS 1
  327. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  328. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  329. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  330. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  331. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  332. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  333. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  334. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  335. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  336. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  337. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  338. #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
  339. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  340. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  341. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  342. #define CONFIG_SYS_FSL_ERRATUM_A004510
  343. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  344. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
  345. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  346. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  347. #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
  348. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  349. #define CONFIG_MAX_CPUS 8
  350. #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
  351. #define CONFIG_SYS_FSL_NUM_LAWS 32
  352. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  353. #define CONFIG_SYS_NUM_FMAN 2
  354. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  355. #define CONFIG_SYS_NUM_FM2_DTSEC 4
  356. #define CONFIG_SYS_NUM_FM1_10GEC 1
  357. #define CONFIG_SYS_NUM_FM2_10GEC 1
  358. #define CONFIG_NUM_DDR_CONTROLLERS 2
  359. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  360. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  361. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
  362. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  363. #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
  364. #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
  365. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  366. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  367. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  368. #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
  369. #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
  370. #define CONFIG_SYS_P4080_ERRATUM_CPU22
  371. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  372. #define CONFIG_SYS_P4080_ERRATUM_SERDES8
  373. #define CONFIG_SYS_P4080_ERRATUM_SERDES9
  374. #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  375. #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
  376. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  377. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  378. #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
  379. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  380. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  381. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  382. #define CONFIG_SYS_FSL_RMU
  383. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  384. #define CONFIG_SYS_FSL_ERRATUM_A004510
  385. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
  386. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
  387. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  388. #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
  389. #define CONFIG_SYS_PPC64 /* 64-bit core */
  390. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  391. #define CONFIG_MAX_CPUS 2
  392. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  393. #define CONFIG_SYS_FSL_NUM_LAWS 32
  394. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  395. #define CONFIG_FSL_SATA_V2
  396. #define CONFIG_SYS_NUM_FMAN 1
  397. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  398. #define CONFIG_SYS_NUM_FM1_10GEC 1
  399. #define CONFIG_NUM_DDR_CONTROLLERS 2
  400. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  401. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  402. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  403. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  404. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  405. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  406. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  407. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  408. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  409. #define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
  410. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  411. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  412. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  413. #define CONFIG_SYS_FSL_ERRATUM_A004510
  414. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  415. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
  416. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  417. #elif defined(CONFIG_PPC_P5040)
  418. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  419. #define CONFIG_MAX_CPUS 4
  420. #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
  421. #define CONFIG_SYS_FSL_NUM_LAWS 32
  422. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  423. #define CONFIG_SYS_NUM_FMAN 2
  424. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  425. #define CONFIG_SYS_NUM_FM1_10GEC 1
  426. #define CONFIG_SYS_NUM_FM2_DTSEC 5
  427. #define CONFIG_SYS_NUM_FM2_10GEC 1
  428. #define CONFIG_NUM_DDR_CONTROLLERS 2
  429. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  430. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  431. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  432. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  433. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  434. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  435. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  436. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  437. #define CONFIG_SYS_FSL_ERRATUM_USB138
  438. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  439. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  440. #define CONFIG_SYS_FSL_ERRATUM_A004699
  441. #define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
  442. #define CONFIG_SYS_FSL_ERRATUM_A004510
  443. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  444. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  445. #elif defined(CONFIG_BSC9131)
  446. #define CONFIG_MAX_CPUS 1
  447. #define CONFIG_FSL_SDHC_V2_3
  448. #define CONFIG_SYS_FSL_NUM_LAWS 12
  449. #define CONFIG_TSECV2
  450. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  451. #define CONFIG_NUM_DDR_CONTROLLERS 1
  452. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
  453. #define CONFIG_NAND_FSL_IFC
  454. #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  455. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  456. #elif defined(CONFIG_PPC_T4240)
  457. #define CONFIG_SYS_PPC64 /* 64-bit core */
  458. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  459. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  460. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  461. #define CONFIG_MAX_CPUS 12
  462. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  463. #define CONFIG_SYS_FSL_NUM_LAWS 32
  464. #define CONFIG_SYS_FSL_SRDS_3
  465. #define CONFIG_SYS_FSL_SRDS_4
  466. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  467. #define CONFIG_SYS_NUM_FMAN 2
  468. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  469. #define CONFIG_SYS_NUM_FM1_10GEC 2
  470. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  471. #define CONFIG_SYS_NUM_FM2_10GEC 2
  472. #define CONFIG_NUM_DDR_CONTROLLERS 3
  473. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  474. #define CONFIG_SYS_FMAN_V3
  475. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  476. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  477. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  478. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  479. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  480. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  481. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  482. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  483. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  484. #define CONFIG_SYS_FSL_ERRATUM_A004468
  485. #define CONFIG_SYS_FSL_ERRATUM_A_004934
  486. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  487. #elif defined(CONFIG_PPC_B4860)
  488. #define CONFIG_SYS_PPC64 /* 64-bit core */
  489. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  490. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  491. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  492. #define CONFIG_MAX_CPUS 4
  493. #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
  494. #define CONFIG_SYS_FSL_NUM_LAWS 32
  495. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  496. #define CONFIG_SYS_NUM_FMAN 1
  497. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  498. #define CONFIG_SYS_NUM_FM1_10GEC 2
  499. #define CONFIG_NUM_DDR_CONTROLLERS 1
  500. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  501. #define CONFIG_SYS_FMAN_V3
  502. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  503. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  504. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  505. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  506. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  507. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  508. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  509. #define CONFIG_SYS_FSL_ERRATUM_A_004934
  510. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
  511. #else
  512. #error Processor type not defined for this platform
  513. #endif
  514. #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
  515. #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
  516. #endif
  517. #endif /* _ASM_MPC85xx_CONFIG_H_ */