cpu.c 6.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297
  1. /*
  2. * Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
  3. * (C) Copyright 2002, 2003 Motorola Inc.
  4. * Xianghua Xiao (X.Xiao@motorola.com)
  5. *
  6. * (C) Copyright 2000
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #include <config.h>
  28. #include <common.h>
  29. #include <watchdog.h>
  30. #include <command.h>
  31. #include <fsl_esdhc.h>
  32. #include <asm/cache.h>
  33. #include <asm/io.h>
  34. DECLARE_GLOBAL_DATA_PTR;
  35. int checkcpu (void)
  36. {
  37. sys_info_t sysinfo;
  38. uint pvr, svr;
  39. uint fam;
  40. uint ver;
  41. uint major, minor;
  42. struct cpu_type *cpu;
  43. char buf1[32], buf2[32];
  44. #ifdef CONFIG_DDR_CLK_FREQ
  45. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  46. u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
  47. >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
  48. #else
  49. u32 ddr_ratio = 0;
  50. #endif
  51. int i;
  52. svr = get_svr();
  53. ver = SVR_SOC_VER(svr);
  54. major = SVR_MAJ(svr);
  55. #ifdef CONFIG_MPC8536
  56. major &= 0x7; /* the msb of this nibble is a mfg code */
  57. #endif
  58. minor = SVR_MIN(svr);
  59. #if (CONFIG_NUM_CPUS > 1)
  60. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
  61. printf("CPU%d: ", pic->whoami);
  62. #else
  63. puts("CPU: ");
  64. #endif
  65. cpu = identify_cpu(ver);
  66. if (cpu) {
  67. puts(cpu->name);
  68. if (IS_E_PROCESSOR(svr))
  69. puts("E");
  70. } else {
  71. puts("Unknown");
  72. }
  73. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  74. pvr = get_pvr();
  75. fam = PVR_FAM(pvr);
  76. ver = PVR_VER(pvr);
  77. major = PVR_MAJ(pvr);
  78. minor = PVR_MIN(pvr);
  79. printf("Core: ");
  80. switch (fam) {
  81. case PVR_FAM(PVR_85xx):
  82. puts("E500");
  83. break;
  84. default:
  85. puts("Unknown");
  86. break;
  87. }
  88. if (PVR_MEM(pvr) == 0x03)
  89. puts("MC");
  90. printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
  91. get_sys_info(&sysinfo);
  92. puts("Clock Configuration:");
  93. for (i = 0; i < CONFIG_NUM_CPUS; i++) {
  94. if (!(i & 3))
  95. printf ("\n ");
  96. printf("CPU%d:%-4s MHz, ",
  97. i,strmhz(buf1, sysinfo.freqProcessor[i]));
  98. }
  99. printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus));
  100. switch (ddr_ratio) {
  101. case 0x0:
  102. printf(" DDR:%-4s MHz (%s MT/s data rate), ",
  103. strmhz(buf1, sysinfo.freqDDRBus/2),
  104. strmhz(buf2, sysinfo.freqDDRBus));
  105. break;
  106. case 0x7:
  107. printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ",
  108. strmhz(buf1, sysinfo.freqDDRBus/2),
  109. strmhz(buf2, sysinfo.freqDDRBus));
  110. break;
  111. default:
  112. printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ",
  113. strmhz(buf1, sysinfo.freqDDRBus/2),
  114. strmhz(buf2, sysinfo.freqDDRBus));
  115. break;
  116. }
  117. if (sysinfo.freqLocalBus > LCRR_CLKDIV)
  118. printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
  119. else
  120. printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
  121. sysinfo.freqLocalBus);
  122. #ifdef CONFIG_CPM2
  123. printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
  124. #endif
  125. #ifdef CONFIG_QE
  126. printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
  127. #endif
  128. puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
  129. return 0;
  130. }
  131. /* ------------------------------------------------------------------------- */
  132. int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
  133. {
  134. uint pvr;
  135. uint ver;
  136. unsigned long val, msr;
  137. pvr = get_pvr();
  138. ver = PVR_VER(pvr);
  139. if (ver & 1){
  140. /* e500 v2 core has reset control register */
  141. volatile unsigned int * rstcr;
  142. rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0);
  143. *rstcr = 0x2; /* HRESET_REQ */
  144. udelay(100);
  145. }
  146. /*
  147. * Fallthrough if the code above failed
  148. * Initiate hard reset in debug control register DBCR0
  149. * Make sure MSR[DE] = 1
  150. */
  151. msr = mfmsr ();
  152. msr |= MSR_DE;
  153. mtmsr (msr);
  154. val = mfspr(DBCR0);
  155. val |= 0x70000000;
  156. mtspr(DBCR0,val);
  157. return 1;
  158. }
  159. /*
  160. * Get timebase clock frequency
  161. */
  162. unsigned long get_tbclk (void)
  163. {
  164. return (gd->bus_clk + 4UL)/8UL;
  165. }
  166. #if defined(CONFIG_WATCHDOG)
  167. void
  168. watchdog_reset(void)
  169. {
  170. int re_enable = disable_interrupts();
  171. reset_85xx_watchdog();
  172. if (re_enable) enable_interrupts();
  173. }
  174. void
  175. reset_85xx_watchdog(void)
  176. {
  177. /*
  178. * Clear TSR(WIS) bit by writing 1
  179. */
  180. unsigned long val;
  181. val = mfspr(SPRN_TSR);
  182. val |= TSR_WIS;
  183. mtspr(SPRN_TSR, val);
  184. }
  185. #endif /* CONFIG_WATCHDOG */
  186. /*
  187. * Configures a UPM. The function requires the respective MxMR to be set
  188. * before calling this function. "size" is the number or entries, not a sizeof.
  189. */
  190. void upmconfig (uint upm, uint * table, uint size)
  191. {
  192. int i, mdr, mad, old_mad = 0;
  193. volatile u32 *mxmr;
  194. volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  195. volatile u32 *brp,*orp;
  196. volatile u8* dummy = NULL;
  197. int upmmask;
  198. switch (upm) {
  199. case UPMA:
  200. mxmr = &lbc->mamr;
  201. upmmask = BR_MS_UPMA;
  202. break;
  203. case UPMB:
  204. mxmr = &lbc->mbmr;
  205. upmmask = BR_MS_UPMB;
  206. break;
  207. case UPMC:
  208. mxmr = &lbc->mcmr;
  209. upmmask = BR_MS_UPMC;
  210. break;
  211. default:
  212. printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm);
  213. hang();
  214. }
  215. /* Find the address for the dummy write transaction */
  216. for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
  217. i++, brp += 2, orp += 2) {
  218. /* Look for a valid BR with selected UPM */
  219. if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
  220. dummy = (volatile u8*)(in_be32(brp) & BR_BA);
  221. break;
  222. }
  223. }
  224. if (i == 8) {
  225. printf("Error: %s() could not find matching BR\n", __FUNCTION__);
  226. hang();
  227. }
  228. for (i = 0; i < size; i++) {
  229. /* 1 */
  230. out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i);
  231. /* 2 */
  232. out_be32(&lbc->mdr, table[i]);
  233. /* 3 */
  234. mdr = in_be32(&lbc->mdr);
  235. /* 4 */
  236. *(volatile u8 *)dummy = 0;
  237. /* 5 */
  238. do {
  239. mad = in_be32(mxmr) & MxMR_MAD_MSK;
  240. } while (mad <= old_mad && !(!mad && i == (size-1)));
  241. old_mad = mad;
  242. }
  243. out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM);
  244. }
  245. /*
  246. * Initializes on-chip MMC controllers.
  247. * to override, implement board_mmc_init()
  248. */
  249. int cpu_mmc_init(bd_t *bis)
  250. {
  251. #ifdef CONFIG_FSL_ESDHC
  252. return fsl_esdhc_mmc_init(bis);
  253. #else
  254. return 0;
  255. #endif
  256. }