timer.c 4.9 KB

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  1. /*
  2. * (C) Copyright 2011
  3. * Marvell Semiconductor <www.marvell.com>
  4. * Written-by: Lei Wen <leiwen@marvell.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22. * MA 02110-1301 USA
  23. */
  24. #include <common.h>
  25. #include <asm/arch/pantheon.h>
  26. /*
  27. * Timer registers
  28. * Refer 6.2.9 in Datasheet
  29. */
  30. struct panthtmr_registers {
  31. u32 clk_ctrl; /* Timer clk control reg */
  32. u32 match[9]; /* Timer match registers */
  33. u32 count[3]; /* Timer count registers */
  34. u32 status[3];
  35. u32 ie[3];
  36. u32 preload[3]; /* Timer preload value */
  37. u32 preload_ctrl[3];
  38. u32 wdt_match_en;
  39. u32 wdt_match_r;
  40. u32 wdt_val;
  41. u32 wdt_sts;
  42. u32 icr[3];
  43. u32 wdt_icr;
  44. u32 cer; /* Timer count enable reg */
  45. u32 cmr;
  46. u32 ilr[3];
  47. u32 wcr;
  48. u32 wfar;
  49. u32 wsar;
  50. u32 cvwr[3];
  51. };
  52. #define TIMER 0 /* Use TIMER 0 */
  53. /* Each timer has 3 match registers */
  54. #define MATCH_CMP(x) ((3 * TIMER) + x)
  55. #define TIMER_LOAD_VAL 0xffffffff
  56. #define COUNT_RD_REQ 0x1
  57. DECLARE_GLOBAL_DATA_PTR;
  58. /* Using gd->tbu from timestamp and gd->tbl for lastdec */
  59. /*
  60. * For preventing risk of instability in reading counter value,
  61. * first set read request to register cvwr and then read same
  62. * register after it captures counter value.
  63. */
  64. ulong read_timer(void)
  65. {
  66. struct panthtmr_registers *panthtimers =
  67. (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
  68. volatile int loop=100;
  69. ulong val;
  70. writel(COUNT_RD_REQ, &panthtimers->cvwr);
  71. while (loop--)
  72. val = readl(&panthtimers->cvwr);
  73. /*
  74. * This stop gcc complain and prevent loop mistake init to 0
  75. */
  76. val = readl(&panthtimers->cvwr);
  77. return val;
  78. }
  79. ulong get_timer_masked(void)
  80. {
  81. ulong now = read_timer();
  82. if (now >= gd->tbl) {
  83. /* normal mode */
  84. gd->tbu += now - gd->tbl;
  85. } else {
  86. /* we have an overflow ... */
  87. gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
  88. }
  89. gd->tbl = now;
  90. return gd->tbu;
  91. }
  92. ulong get_timer(ulong base)
  93. {
  94. return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
  95. base);
  96. }
  97. void __udelay(unsigned long usec)
  98. {
  99. ulong delayticks;
  100. ulong endtime;
  101. delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
  102. endtime = get_timer_masked() + delayticks;
  103. while (get_timer_masked() < endtime)
  104. ;
  105. }
  106. /*
  107. * init the Timer
  108. */
  109. int timer_init(void)
  110. {
  111. struct panthapb_registers *apb1clkres =
  112. (struct panthapb_registers *) PANTHEON_APBC_BASE;
  113. struct panthtmr_registers *panthtimers =
  114. (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
  115. /* Enable Timer clock at 3.25 MHZ */
  116. writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
  117. /* load value into timer */
  118. writel(0x0, &panthtimers->clk_ctrl);
  119. /* Use Timer 0 Match Resiger 0 */
  120. writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
  121. /* Preload value is 0 */
  122. writel(0x0, &panthtimers->preload[TIMER]);
  123. /* Enable match comparator 0 for Timer 0 */
  124. writel(0x1, &panthtimers->preload_ctrl[TIMER]);
  125. /* Enable timer 0 */
  126. writel(0x1, &panthtimers->cer);
  127. /* init the gd->tbu and gd->tbl value */
  128. gd->tbl = read_timer();
  129. gd->tbu = 0;
  130. return 0;
  131. }
  132. #define MPMU_APRR_WDTR (1<<4)
  133. #define TMR_WFAR 0xbaba /* WDT Register First key */
  134. #define TMP_WSAR 0xeb10 /* WDT Register Second key */
  135. /*
  136. * This function uses internal Watchdog Timer
  137. * based reset mechanism.
  138. * Steps to write watchdog registers (protected access)
  139. * 1. Write key value to TMR_WFAR reg.
  140. * 2. Write key value to TMP_WSAR reg.
  141. * 3. Perform write operation.
  142. */
  143. void reset_cpu (unsigned long ignored)
  144. {
  145. struct panthmpmu_registers *mpmu =
  146. (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
  147. struct panthtmr_registers *panthtimers =
  148. (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
  149. u32 val;
  150. /* negate hardware reset to the WDT after system reset */
  151. val = readl(&mpmu->aprr);
  152. val = val | MPMU_APRR_WDTR;
  153. writel(val, &mpmu->aprr);
  154. /* reset/enable WDT clock */
  155. writel(APBC_APBCLK, &mpmu->wdtpcr);
  156. /* clear previous WDT status */
  157. writel(TMR_WFAR, &panthtimers->wfar);
  158. writel(TMP_WSAR, &panthtimers->wsar);
  159. writel(0, &panthtimers->wdt_sts);
  160. /* set match counter */
  161. writel(TMR_WFAR, &panthtimers->wfar);
  162. writel(TMP_WSAR, &panthtimers->wsar);
  163. writel(0xf, &panthtimers->wdt_match_r);
  164. /* enable WDT reset */
  165. writel(TMR_WFAR, &panthtimers->wfar);
  166. writel(TMP_WSAR, &panthtimers->wsar);
  167. writel(0x3, &panthtimers->wdt_match_en);
  168. /*enable functional WDT clock */
  169. writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
  170. }