sysreset_rk3368.c 1.4 KB

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  1. /*
  2. * (C) Copyright Rockchip Electronics Co., Ltd
  3. *
  4. * SPDX-License-Identifier: GPL-2.0
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <sysreset.h>
  10. #include <asm/io.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/cru_rk3368.h>
  13. #include <asm/arch/hardware.h>
  14. #include <linux/err.h>
  15. static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru)
  16. {
  17. struct rk3368_pll *pll;
  18. int i;
  19. for (i = 0; i < 6; i++) {
  20. pll = &cru->pll[i];
  21. rk_clrreg(&pll->con3, PLL_MODE_MASK);
  22. }
  23. }
  24. static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type)
  25. {
  26. struct rk3368_cru *cru = rockchip_get_cru();
  27. if (IS_ERR(cru))
  28. return PTR_ERR(cru);
  29. switch (type) {
  30. case SYSRESET_WARM:
  31. rk3368_pll_enter_slow_mode(cru);
  32. rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
  33. PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
  34. writel(0xeca8, &cru->glb_srst_snd_val);
  35. break;
  36. case SYSRESET_COLD:
  37. rk3368_pll_enter_slow_mode(cru);
  38. rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK,
  39. PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT);
  40. writel(0xfdb9, &cru->glb_srst_fst_val);
  41. break;
  42. default:
  43. return -EPROTONOSUPPORT;
  44. }
  45. return -EINPROGRESS;
  46. }
  47. static struct sysreset_ops rk3368_sysreset = {
  48. .request = rk3368_sysreset_request,
  49. };
  50. U_BOOT_DRIVER(sysreset_rk3368) = {
  51. .name = "rk3368_sysreset",
  52. .id = UCLASS_SYSRESET,
  53. .ops = &rk3368_sysreset,
  54. };