atmel_nand.c 39 KB

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  1. /*
  2. * (C) Copyright 2007-2008
  3. * Stelian Pop <stelian@popies.net>
  4. * Lead Tech Design <www.leadtechdesign.com>
  5. *
  6. * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  7. *
  8. * Add Programmable Multibit ECC support for various AT91 SoC
  9. * (C) Copyright 2012 ATMEL, Hong Xu
  10. *
  11. * SPDX-License-Identifier: GPL-2.0+
  12. */
  13. #include <common.h>
  14. #include <asm/gpio.h>
  15. #include <asm/arch/gpio.h>
  16. #include <malloc.h>
  17. #include <nand.h>
  18. #include <watchdog.h>
  19. #include <linux/mtd/nand_ecc.h>
  20. #ifdef CONFIG_ATMEL_NAND_HWECC
  21. /* Register access macros */
  22. #define ecc_readl(add, reg) \
  23. readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
  24. #define ecc_writel(add, reg, value) \
  25. writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
  26. #include "atmel_nand_ecc.h" /* Hardware ECC registers */
  27. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  28. #ifdef CONFIG_SPL_BUILD
  29. #undef CONFIG_SYS_NAND_ONFI_DETECTION
  30. #endif
  31. struct atmel_nand_host {
  32. struct pmecc_regs __iomem *pmecc;
  33. struct pmecc_errloc_regs __iomem *pmerrloc;
  34. void __iomem *pmecc_rom_base;
  35. u8 pmecc_corr_cap;
  36. u16 pmecc_sector_size;
  37. u32 pmecc_index_table_offset;
  38. u32 pmecc_version;
  39. int pmecc_bytes_per_sector;
  40. int pmecc_sector_number;
  41. int pmecc_degree; /* Degree of remainders */
  42. int pmecc_cw_len; /* Length of codeword */
  43. /* lookup table for alpha_to and index_of */
  44. void __iomem *pmecc_alpha_to;
  45. void __iomem *pmecc_index_of;
  46. /* data for pmecc computation */
  47. int16_t *pmecc_smu;
  48. int16_t *pmecc_partial_syn;
  49. int16_t *pmecc_si;
  50. int16_t *pmecc_lmu; /* polynomal order */
  51. int *pmecc_mu;
  52. int *pmecc_dmu;
  53. int *pmecc_delta;
  54. };
  55. static struct atmel_nand_host pmecc_host;
  56. static struct nand_ecclayout atmel_pmecc_oobinfo;
  57. /*
  58. * Return number of ecc bytes per sector according to sector size and
  59. * correction capability
  60. *
  61. * Following table shows what at91 PMECC supported:
  62. * Correction Capability Sector_512_bytes Sector_1024_bytes
  63. * ===================== ================ =================
  64. * 2-bits 4-bytes 4-bytes
  65. * 4-bits 7-bytes 7-bytes
  66. * 8-bits 13-bytes 14-bytes
  67. * 12-bits 20-bytes 21-bytes
  68. * 24-bits 39-bytes 42-bytes
  69. * 32-bits 52-bytes 56-bytes
  70. */
  71. static int pmecc_get_ecc_bytes(int cap, int sector_size)
  72. {
  73. int m = 12 + sector_size / 512;
  74. return (m * cap + 7) / 8;
  75. }
  76. static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
  77. int oobsize, int ecc_len)
  78. {
  79. int i;
  80. layout->eccbytes = ecc_len;
  81. /* ECC will occupy the last ecc_len bytes continuously */
  82. for (i = 0; i < ecc_len; i++)
  83. layout->eccpos[i] = oobsize - ecc_len + i;
  84. layout->oobfree[0].offset = 2;
  85. layout->oobfree[0].length =
  86. oobsize - ecc_len - layout->oobfree[0].offset;
  87. }
  88. static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
  89. {
  90. int table_size;
  91. table_size = host->pmecc_sector_size == 512 ?
  92. PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
  93. /* the ALPHA lookup table is right behind the INDEX lookup table. */
  94. return host->pmecc_rom_base + host->pmecc_index_table_offset +
  95. table_size * sizeof(int16_t);
  96. }
  97. static void pmecc_data_free(struct atmel_nand_host *host)
  98. {
  99. free(host->pmecc_partial_syn);
  100. free(host->pmecc_si);
  101. free(host->pmecc_lmu);
  102. free(host->pmecc_smu);
  103. free(host->pmecc_mu);
  104. free(host->pmecc_dmu);
  105. free(host->pmecc_delta);
  106. }
  107. static int pmecc_data_alloc(struct atmel_nand_host *host)
  108. {
  109. const int cap = host->pmecc_corr_cap;
  110. int size;
  111. size = (2 * cap + 1) * sizeof(int16_t);
  112. host->pmecc_partial_syn = malloc(size);
  113. host->pmecc_si = malloc(size);
  114. host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
  115. host->pmecc_smu = malloc((cap + 2) * size);
  116. size = (cap + 1) * sizeof(int);
  117. host->pmecc_mu = malloc(size);
  118. host->pmecc_dmu = malloc(size);
  119. host->pmecc_delta = malloc(size);
  120. if (host->pmecc_partial_syn &&
  121. host->pmecc_si &&
  122. host->pmecc_lmu &&
  123. host->pmecc_smu &&
  124. host->pmecc_mu &&
  125. host->pmecc_dmu &&
  126. host->pmecc_delta)
  127. return 0;
  128. /* error happened */
  129. pmecc_data_free(host);
  130. return -ENOMEM;
  131. }
  132. static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
  133. {
  134. struct nand_chip *nand_chip = mtd->priv;
  135. struct atmel_nand_host *host = nand_chip->priv;
  136. int i;
  137. uint32_t value;
  138. /* Fill odd syndromes */
  139. for (i = 0; i < host->pmecc_corr_cap; i++) {
  140. value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
  141. if (i & 1)
  142. value >>= 16;
  143. value &= 0xffff;
  144. host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
  145. }
  146. }
  147. static void pmecc_substitute(struct mtd_info *mtd)
  148. {
  149. struct nand_chip *nand_chip = mtd->priv;
  150. struct atmel_nand_host *host = nand_chip->priv;
  151. int16_t __iomem *alpha_to = host->pmecc_alpha_to;
  152. int16_t __iomem *index_of = host->pmecc_index_of;
  153. int16_t *partial_syn = host->pmecc_partial_syn;
  154. const int cap = host->pmecc_corr_cap;
  155. int16_t *si;
  156. int i, j;
  157. /* si[] is a table that holds the current syndrome value,
  158. * an element of that table belongs to the field
  159. */
  160. si = host->pmecc_si;
  161. memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
  162. /* Computation 2t syndromes based on S(x) */
  163. /* Odd syndromes */
  164. for (i = 1; i < 2 * cap; i += 2) {
  165. for (j = 0; j < host->pmecc_degree; j++) {
  166. if (partial_syn[i] & (0x1 << j))
  167. si[i] = readw(alpha_to + i * j) ^ si[i];
  168. }
  169. }
  170. /* Even syndrome = (Odd syndrome) ** 2 */
  171. for (i = 2, j = 1; j <= cap; i = ++j << 1) {
  172. if (si[j] == 0) {
  173. si[i] = 0;
  174. } else {
  175. int16_t tmp;
  176. tmp = readw(index_of + si[j]);
  177. tmp = (tmp * 2) % host->pmecc_cw_len;
  178. si[i] = readw(alpha_to + tmp);
  179. }
  180. }
  181. }
  182. /*
  183. * This function defines a Berlekamp iterative procedure for
  184. * finding the value of the error location polynomial.
  185. * The input is si[], initialize by pmecc_substitute().
  186. * The output is smu[][].
  187. *
  188. * This function is written according to chip datasheet Chapter:
  189. * Find the Error Location Polynomial Sigma(x) of Section:
  190. * Programmable Multibit ECC Control (PMECC).
  191. */
  192. static void pmecc_get_sigma(struct mtd_info *mtd)
  193. {
  194. struct nand_chip *nand_chip = mtd->priv;
  195. struct atmel_nand_host *host = nand_chip->priv;
  196. int16_t *lmu = host->pmecc_lmu;
  197. int16_t *si = host->pmecc_si;
  198. int *mu = host->pmecc_mu;
  199. int *dmu = host->pmecc_dmu; /* Discrepancy */
  200. int *delta = host->pmecc_delta; /* Delta order */
  201. int cw_len = host->pmecc_cw_len;
  202. const int16_t cap = host->pmecc_corr_cap;
  203. const int num = 2 * cap + 1;
  204. int16_t __iomem *index_of = host->pmecc_index_of;
  205. int16_t __iomem *alpha_to = host->pmecc_alpha_to;
  206. int i, j, k;
  207. uint32_t dmu_0_count, tmp;
  208. int16_t *smu = host->pmecc_smu;
  209. /* index of largest delta */
  210. int ro;
  211. int largest;
  212. int diff;
  213. /* Init the Sigma(x) */
  214. memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
  215. dmu_0_count = 0;
  216. /* First Row */
  217. /* Mu */
  218. mu[0] = -1;
  219. smu[0] = 1;
  220. /* discrepancy set to 1 */
  221. dmu[0] = 1;
  222. /* polynom order set to 0 */
  223. lmu[0] = 0;
  224. /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
  225. delta[0] = -1;
  226. /* Second Row */
  227. /* Mu */
  228. mu[1] = 0;
  229. /* Sigma(x) set to 1 */
  230. smu[num] = 1;
  231. /* discrepancy set to S1 */
  232. dmu[1] = si[1];
  233. /* polynom order set to 0 */
  234. lmu[1] = 0;
  235. /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
  236. delta[1] = 0;
  237. for (i = 1; i <= cap; i++) {
  238. mu[i + 1] = i << 1;
  239. /* Begin Computing Sigma (Mu+1) and L(mu) */
  240. /* check if discrepancy is set to 0 */
  241. if (dmu[i] == 0) {
  242. dmu_0_count++;
  243. tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
  244. if ((cap - (lmu[i] >> 1) - 1) & 0x1)
  245. tmp += 2;
  246. else
  247. tmp += 1;
  248. if (dmu_0_count == tmp) {
  249. for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
  250. smu[(cap + 1) * num + j] =
  251. smu[i * num + j];
  252. lmu[cap + 1] = lmu[i];
  253. return;
  254. }
  255. /* copy polynom */
  256. for (j = 0; j <= lmu[i] >> 1; j++)
  257. smu[(i + 1) * num + j] = smu[i * num + j];
  258. /* copy previous polynom order to the next */
  259. lmu[i + 1] = lmu[i];
  260. } else {
  261. ro = 0;
  262. largest = -1;
  263. /* find largest delta with dmu != 0 */
  264. for (j = 0; j < i; j++) {
  265. if ((dmu[j]) && (delta[j] > largest)) {
  266. largest = delta[j];
  267. ro = j;
  268. }
  269. }
  270. /* compute difference */
  271. diff = (mu[i] - mu[ro]);
  272. /* Compute degree of the new smu polynomial */
  273. if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
  274. lmu[i + 1] = lmu[i];
  275. else
  276. lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
  277. /* Init smu[i+1] with 0 */
  278. for (k = 0; k < num; k++)
  279. smu[(i + 1) * num + k] = 0;
  280. /* Compute smu[i+1] */
  281. for (k = 0; k <= lmu[ro] >> 1; k++) {
  282. int16_t a, b, c;
  283. if (!(smu[ro * num + k] && dmu[i]))
  284. continue;
  285. a = readw(index_of + dmu[i]);
  286. b = readw(index_of + dmu[ro]);
  287. c = readw(index_of + smu[ro * num + k]);
  288. tmp = a + (cw_len - b) + c;
  289. a = readw(alpha_to + tmp % cw_len);
  290. smu[(i + 1) * num + (k + diff)] = a;
  291. }
  292. for (k = 0; k <= lmu[i] >> 1; k++)
  293. smu[(i + 1) * num + k] ^= smu[i * num + k];
  294. }
  295. /* End Computing Sigma (Mu+1) and L(mu) */
  296. /* In either case compute delta */
  297. delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
  298. /* Do not compute discrepancy for the last iteration */
  299. if (i >= cap)
  300. continue;
  301. for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
  302. tmp = 2 * (i - 1);
  303. if (k == 0) {
  304. dmu[i + 1] = si[tmp + 3];
  305. } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
  306. int16_t a, b, c;
  307. a = readw(index_of +
  308. smu[(i + 1) * num + k]);
  309. b = si[2 * (i - 1) + 3 - k];
  310. c = readw(index_of + b);
  311. tmp = a + c;
  312. tmp %= cw_len;
  313. dmu[i + 1] = readw(alpha_to + tmp) ^
  314. dmu[i + 1];
  315. }
  316. }
  317. }
  318. }
  319. static int pmecc_err_location(struct mtd_info *mtd)
  320. {
  321. struct nand_chip *nand_chip = mtd->priv;
  322. struct atmel_nand_host *host = nand_chip->priv;
  323. const int cap = host->pmecc_corr_cap;
  324. const int num = 2 * cap + 1;
  325. int sector_size = host->pmecc_sector_size;
  326. int err_nbr = 0; /* number of error */
  327. int roots_nbr; /* number of roots */
  328. int i;
  329. uint32_t val;
  330. int16_t *smu = host->pmecc_smu;
  331. int timeout = PMECC_MAX_TIMEOUT_US;
  332. pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
  333. for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
  334. pmecc_writel(host->pmerrloc, sigma[i],
  335. smu[(cap + 1) * num + i]);
  336. err_nbr++;
  337. }
  338. val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
  339. if (sector_size == 1024)
  340. val |= PMERRLOC_ELCFG_SECTOR_1024;
  341. pmecc_writel(host->pmerrloc, elcfg, val);
  342. pmecc_writel(host->pmerrloc, elen,
  343. sector_size * 8 + host->pmecc_degree * cap);
  344. while (--timeout) {
  345. if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
  346. break;
  347. WATCHDOG_RESET();
  348. udelay(1);
  349. }
  350. if (!timeout) {
  351. dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
  352. return -1;
  353. }
  354. roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
  355. >> 8;
  356. /* Number of roots == degree of smu hence <= cap */
  357. if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
  358. return err_nbr - 1;
  359. /* Number of roots does not match the degree of smu
  360. * unable to correct error */
  361. return -1;
  362. }
  363. static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
  364. int sector_num, int extra_bytes, int err_nbr)
  365. {
  366. struct nand_chip *nand_chip = mtd->priv;
  367. struct atmel_nand_host *host = nand_chip->priv;
  368. int i = 0;
  369. int byte_pos, bit_pos, sector_size, pos;
  370. uint32_t tmp;
  371. uint8_t err_byte;
  372. sector_size = host->pmecc_sector_size;
  373. while (err_nbr) {
  374. tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
  375. byte_pos = tmp / 8;
  376. bit_pos = tmp % 8;
  377. if (byte_pos >= (sector_size + extra_bytes))
  378. BUG(); /* should never happen */
  379. if (byte_pos < sector_size) {
  380. err_byte = *(buf + byte_pos);
  381. *(buf + byte_pos) ^= (1 << bit_pos);
  382. pos = sector_num * host->pmecc_sector_size + byte_pos;
  383. dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
  384. pos, bit_pos, err_byte, *(buf + byte_pos));
  385. } else {
  386. /* Bit flip in OOB area */
  387. tmp = sector_num * host->pmecc_bytes_per_sector
  388. + (byte_pos - sector_size);
  389. err_byte = ecc[tmp];
  390. ecc[tmp] ^= (1 << bit_pos);
  391. pos = tmp + nand_chip->ecc.layout->eccpos[0];
  392. dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
  393. pos, bit_pos, err_byte, ecc[tmp]);
  394. }
  395. i++;
  396. err_nbr--;
  397. }
  398. return;
  399. }
  400. static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
  401. u8 *ecc)
  402. {
  403. struct nand_chip *nand_chip = mtd->priv;
  404. struct atmel_nand_host *host = nand_chip->priv;
  405. int i, err_nbr, eccbytes;
  406. uint8_t *buf_pos;
  407. /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
  408. if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
  409. goto normal_check;
  410. eccbytes = nand_chip->ecc.bytes;
  411. for (i = 0; i < eccbytes; i++)
  412. if (ecc[i] != 0xff)
  413. goto normal_check;
  414. /* Erased page, return OK */
  415. return 0;
  416. normal_check:
  417. for (i = 0; i < host->pmecc_sector_number; i++) {
  418. err_nbr = 0;
  419. if (pmecc_stat & 0x1) {
  420. buf_pos = buf + i * host->pmecc_sector_size;
  421. pmecc_gen_syndrome(mtd, i);
  422. pmecc_substitute(mtd);
  423. pmecc_get_sigma(mtd);
  424. err_nbr = pmecc_err_location(mtd);
  425. if (err_nbr == -1) {
  426. dev_err(host->dev, "PMECC: Too many errors\n");
  427. mtd->ecc_stats.failed++;
  428. return -EIO;
  429. } else {
  430. pmecc_correct_data(mtd, buf_pos, ecc, i,
  431. host->pmecc_bytes_per_sector, err_nbr);
  432. mtd->ecc_stats.corrected += err_nbr;
  433. }
  434. }
  435. pmecc_stat >>= 1;
  436. }
  437. return 0;
  438. }
  439. static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
  440. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  441. {
  442. struct atmel_nand_host *host = chip->priv;
  443. int eccsize = chip->ecc.size;
  444. uint8_t *oob = chip->oob_poi;
  445. uint32_t *eccpos = chip->ecc.layout->eccpos;
  446. uint32_t stat;
  447. int timeout = PMECC_MAX_TIMEOUT_US;
  448. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  449. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  450. pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
  451. & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
  452. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  453. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
  454. chip->read_buf(mtd, buf, eccsize);
  455. chip->read_buf(mtd, oob, mtd->oobsize);
  456. while (--timeout) {
  457. if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
  458. break;
  459. WATCHDOG_RESET();
  460. udelay(1);
  461. }
  462. if (!timeout) {
  463. dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
  464. return -1;
  465. }
  466. stat = pmecc_readl(host->pmecc, isr);
  467. if (stat != 0)
  468. if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
  469. return -EIO;
  470. return 0;
  471. }
  472. static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
  473. struct nand_chip *chip, const uint8_t *buf,
  474. int oob_required)
  475. {
  476. struct atmel_nand_host *host = chip->priv;
  477. uint32_t *eccpos = chip->ecc.layout->eccpos;
  478. int i, j;
  479. int timeout = PMECC_MAX_TIMEOUT_US;
  480. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  481. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  482. pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
  483. PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
  484. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  485. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
  486. chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
  487. while (--timeout) {
  488. if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
  489. break;
  490. WATCHDOG_RESET();
  491. udelay(1);
  492. }
  493. if (!timeout) {
  494. dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
  495. goto out;
  496. }
  497. for (i = 0; i < host->pmecc_sector_number; i++) {
  498. for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
  499. int pos;
  500. pos = i * host->pmecc_bytes_per_sector + j;
  501. chip->oob_poi[eccpos[pos]] =
  502. pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
  503. }
  504. }
  505. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  506. out:
  507. return 0;
  508. }
  509. static void atmel_pmecc_core_init(struct mtd_info *mtd)
  510. {
  511. struct nand_chip *nand_chip = mtd->priv;
  512. struct atmel_nand_host *host = nand_chip->priv;
  513. uint32_t val = 0;
  514. struct nand_ecclayout *ecc_layout;
  515. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
  516. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
  517. switch (host->pmecc_corr_cap) {
  518. case 2:
  519. val = PMECC_CFG_BCH_ERR2;
  520. break;
  521. case 4:
  522. val = PMECC_CFG_BCH_ERR4;
  523. break;
  524. case 8:
  525. val = PMECC_CFG_BCH_ERR8;
  526. break;
  527. case 12:
  528. val = PMECC_CFG_BCH_ERR12;
  529. break;
  530. case 24:
  531. val = PMECC_CFG_BCH_ERR24;
  532. break;
  533. case 32:
  534. val = PMECC_CFG_BCH_ERR32;
  535. break;
  536. }
  537. if (host->pmecc_sector_size == 512)
  538. val |= PMECC_CFG_SECTOR512;
  539. else if (host->pmecc_sector_size == 1024)
  540. val |= PMECC_CFG_SECTOR1024;
  541. switch (host->pmecc_sector_number) {
  542. case 1:
  543. val |= PMECC_CFG_PAGE_1SECTOR;
  544. break;
  545. case 2:
  546. val |= PMECC_CFG_PAGE_2SECTORS;
  547. break;
  548. case 4:
  549. val |= PMECC_CFG_PAGE_4SECTORS;
  550. break;
  551. case 8:
  552. val |= PMECC_CFG_PAGE_8SECTORS;
  553. break;
  554. }
  555. val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
  556. | PMECC_CFG_AUTO_DISABLE);
  557. pmecc_writel(host->pmecc, cfg, val);
  558. ecc_layout = nand_chip->ecc.layout;
  559. pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
  560. pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
  561. pmecc_writel(host->pmecc, eaddr,
  562. ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
  563. /* See datasheet about PMECC Clock Control Register */
  564. pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
  565. pmecc_writel(host->pmecc, idr, 0xff);
  566. pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
  567. }
  568. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  569. /*
  570. * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
  571. * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
  572. * ONFI ECC parameters.
  573. * @host: point to an atmel_nand_host structure.
  574. * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
  575. * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
  576. * @chip: point to an nand_chip structure.
  577. * @cap: store the ONFI ECC correct bits capbility
  578. * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
  579. *
  580. * Return 0 if success. otherwise return the error code.
  581. */
  582. static int pmecc_choose_ecc(struct atmel_nand_host *host,
  583. struct nand_chip *chip,
  584. int *cap, int *sector_size)
  585. {
  586. /* Get ECC requirement from ONFI parameters */
  587. *cap = *sector_size = 0;
  588. if (chip->onfi_version) {
  589. *cap = chip->ecc_strength_ds;
  590. *sector_size = chip->ecc_step_ds;
  591. MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
  592. *cap, *sector_size);
  593. }
  594. if (*cap == 0 && *sector_size == 0) {
  595. /* Non-ONFI compliant */
  596. dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes\n");
  597. *cap = 2;
  598. *sector_size = 512;
  599. }
  600. /* If head file doesn't specify then use the one in ONFI parameters */
  601. if (host->pmecc_corr_cap == 0) {
  602. /* use the most fitable ecc bits (the near bigger one ) */
  603. if (*cap <= 2)
  604. host->pmecc_corr_cap = 2;
  605. else if (*cap <= 4)
  606. host->pmecc_corr_cap = 4;
  607. else if (*cap <= 8)
  608. host->pmecc_corr_cap = 8;
  609. else if (*cap <= 12)
  610. host->pmecc_corr_cap = 12;
  611. else if (*cap <= 24)
  612. host->pmecc_corr_cap = 24;
  613. else
  614. #ifdef CONFIG_SAMA5D2
  615. host->pmecc_corr_cap = 32;
  616. #else
  617. host->pmecc_corr_cap = 24;
  618. #endif
  619. }
  620. if (host->pmecc_sector_size == 0) {
  621. /* use the most fitable sector size (the near smaller one ) */
  622. if (*sector_size >= 1024)
  623. host->pmecc_sector_size = 1024;
  624. else if (*sector_size >= 512)
  625. host->pmecc_sector_size = 512;
  626. else
  627. return -EINVAL;
  628. }
  629. return 0;
  630. }
  631. #endif
  632. #if defined(NO_GALOIS_TABLE_IN_ROM)
  633. static uint16_t *pmecc_galois_table;
  634. static inline int deg(unsigned int poly)
  635. {
  636. /* polynomial degree is the most-significant bit index */
  637. return fls(poly) - 1;
  638. }
  639. static int build_gf_tables(int mm, unsigned int poly,
  640. int16_t *index_of, int16_t *alpha_to)
  641. {
  642. unsigned int i, x = 1;
  643. const unsigned int k = 1 << deg(poly);
  644. unsigned int nn = (1 << mm) - 1;
  645. /* primitive polynomial must be of degree m */
  646. if (k != (1u << mm))
  647. return -EINVAL;
  648. for (i = 0; i < nn; i++) {
  649. alpha_to[i] = x;
  650. index_of[x] = i;
  651. if (i && (x == 1))
  652. /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
  653. return -EINVAL;
  654. x <<= 1;
  655. if (x & k)
  656. x ^= poly;
  657. }
  658. alpha_to[nn] = 1;
  659. index_of[0] = 0;
  660. return 0;
  661. }
  662. static uint16_t *create_lookup_table(int sector_size)
  663. {
  664. int degree = (sector_size == 512) ?
  665. PMECC_GF_DIMENSION_13 :
  666. PMECC_GF_DIMENSION_14;
  667. unsigned int poly = (sector_size == 512) ?
  668. PMECC_GF_13_PRIMITIVE_POLY :
  669. PMECC_GF_14_PRIMITIVE_POLY;
  670. int table_size = (sector_size == 512) ?
  671. PMECC_INDEX_TABLE_SIZE_512 :
  672. PMECC_INDEX_TABLE_SIZE_1024;
  673. int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
  674. if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
  675. return NULL;
  676. return (uint16_t *)addr;
  677. }
  678. #endif
  679. static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
  680. struct mtd_info *mtd)
  681. {
  682. struct atmel_nand_host *host;
  683. int cap, sector_size;
  684. host = nand->priv = &pmecc_host;
  685. nand->ecc.mode = NAND_ECC_HW;
  686. nand->ecc.calculate = NULL;
  687. nand->ecc.correct = NULL;
  688. nand->ecc.hwctl = NULL;
  689. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  690. host->pmecc_corr_cap = host->pmecc_sector_size = 0;
  691. #ifdef CONFIG_PMECC_CAP
  692. host->pmecc_corr_cap = CONFIG_PMECC_CAP;
  693. #endif
  694. #ifdef CONFIG_PMECC_SECTOR_SIZE
  695. host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
  696. #endif
  697. /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
  698. * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
  699. * from ONFI.
  700. */
  701. if (pmecc_choose_ecc(host, nand, &cap, &sector_size)) {
  702. dev_err(host->dev, "Required ECC %d bits in %d bytes not supported!\n",
  703. cap, sector_size);
  704. return -EINVAL;
  705. }
  706. if (cap > host->pmecc_corr_cap)
  707. dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
  708. host->pmecc_corr_cap, cap);
  709. if (sector_size < host->pmecc_sector_size)
  710. dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
  711. host->pmecc_sector_size, sector_size);
  712. #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
  713. host->pmecc_corr_cap = CONFIG_PMECC_CAP;
  714. host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
  715. #endif
  716. cap = host->pmecc_corr_cap;
  717. sector_size = host->pmecc_sector_size;
  718. /* TODO: need check whether cap & sector_size is validate */
  719. #if defined(NO_GALOIS_TABLE_IN_ROM)
  720. /*
  721. * As pmecc_rom_base is the begin of the gallois field table, So the
  722. * index offset just set as 0.
  723. */
  724. host->pmecc_index_table_offset = 0;
  725. #else
  726. if (host->pmecc_sector_size == 512)
  727. host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
  728. else
  729. host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
  730. #endif
  731. MTDDEBUG(MTD_DEBUG_LEVEL1,
  732. "Initialize PMECC params, cap: %d, sector: %d\n",
  733. cap, sector_size);
  734. host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
  735. host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
  736. ATMEL_BASE_PMERRLOC;
  737. #if defined(NO_GALOIS_TABLE_IN_ROM)
  738. pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
  739. if (!pmecc_galois_table) {
  740. dev_err(host->dev, "out of memory\n");
  741. return -ENOMEM;
  742. }
  743. host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
  744. #else
  745. host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
  746. #endif
  747. /* ECC is calculated for the whole page (1 step) */
  748. nand->ecc.size = mtd->writesize;
  749. /* set ECC page size and oob layout */
  750. switch (mtd->writesize) {
  751. case 2048:
  752. case 4096:
  753. case 8192:
  754. host->pmecc_degree = (sector_size == 512) ?
  755. PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
  756. host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
  757. host->pmecc_sector_number = mtd->writesize / sector_size;
  758. host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
  759. cap, sector_size);
  760. host->pmecc_alpha_to = pmecc_get_alpha_to(host);
  761. host->pmecc_index_of = host->pmecc_rom_base +
  762. host->pmecc_index_table_offset;
  763. nand->ecc.steps = 1;
  764. nand->ecc.bytes = host->pmecc_bytes_per_sector *
  765. host->pmecc_sector_number;
  766. if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
  767. dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
  768. MTD_MAX_ECCPOS_ENTRIES_LARGE);
  769. return -EINVAL;
  770. }
  771. if (nand->ecc.bytes > mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
  772. dev_err(host->dev, "No room for ECC bytes\n");
  773. return -EINVAL;
  774. }
  775. pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
  776. mtd->oobsize,
  777. nand->ecc.bytes);
  778. nand->ecc.layout = &atmel_pmecc_oobinfo;
  779. break;
  780. case 512:
  781. case 1024:
  782. /* TODO */
  783. dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
  784. default:
  785. /* page size not handled by HW ECC */
  786. /* switching back to soft ECC */
  787. nand->ecc.mode = NAND_ECC_SOFT;
  788. nand->ecc.read_page = NULL;
  789. nand->ecc.postpad = 0;
  790. nand->ecc.prepad = 0;
  791. nand->ecc.bytes = 0;
  792. return 0;
  793. }
  794. /* Allocate data for PMECC computation */
  795. if (pmecc_data_alloc(host)) {
  796. dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
  797. return -ENOMEM;
  798. }
  799. nand->options |= NAND_NO_SUBPAGE_WRITE;
  800. nand->ecc.read_page = atmel_nand_pmecc_read_page;
  801. nand->ecc.write_page = atmel_nand_pmecc_write_page;
  802. nand->ecc.strength = cap;
  803. /* Check the PMECC ip version */
  804. host->pmecc_version = pmecc_readl(host->pmerrloc, version);
  805. dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
  806. atmel_pmecc_core_init(mtd);
  807. return 0;
  808. }
  809. #else
  810. /* oob layout for large page size
  811. * bad block info is on bytes 0 and 1
  812. * the bytes have to be consecutives to avoid
  813. * several NAND_CMD_RNDOUT during read
  814. */
  815. static struct nand_ecclayout atmel_oobinfo_large = {
  816. .eccbytes = 4,
  817. .eccpos = {60, 61, 62, 63},
  818. .oobfree = {
  819. {2, 58}
  820. },
  821. };
  822. /* oob layout for small page size
  823. * bad block info is on bytes 4 and 5
  824. * the bytes have to be consecutives to avoid
  825. * several NAND_CMD_RNDOUT during read
  826. */
  827. static struct nand_ecclayout atmel_oobinfo_small = {
  828. .eccbytes = 4,
  829. .eccpos = {0, 1, 2, 3},
  830. .oobfree = {
  831. {6, 10}
  832. },
  833. };
  834. /*
  835. * Calculate HW ECC
  836. *
  837. * function called after a write
  838. *
  839. * mtd: MTD block structure
  840. * dat: raw data (unused)
  841. * ecc_code: buffer for ECC
  842. */
  843. static int atmel_nand_calculate(struct mtd_info *mtd,
  844. const u_char *dat, unsigned char *ecc_code)
  845. {
  846. unsigned int ecc_value;
  847. /* get the first 2 ECC bytes */
  848. ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
  849. ecc_code[0] = ecc_value & 0xFF;
  850. ecc_code[1] = (ecc_value >> 8) & 0xFF;
  851. /* get the last 2 ECC bytes */
  852. ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
  853. ecc_code[2] = ecc_value & 0xFF;
  854. ecc_code[3] = (ecc_value >> 8) & 0xFF;
  855. return 0;
  856. }
  857. /*
  858. * HW ECC read page function
  859. *
  860. * mtd: mtd info structure
  861. * chip: nand chip info structure
  862. * buf: buffer to store read data
  863. * oob_required: caller expects OOB data read to chip->oob_poi
  864. */
  865. static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  866. uint8_t *buf, int oob_required, int page)
  867. {
  868. int eccsize = chip->ecc.size;
  869. int eccbytes = chip->ecc.bytes;
  870. uint32_t *eccpos = chip->ecc.layout->eccpos;
  871. uint8_t *p = buf;
  872. uint8_t *oob = chip->oob_poi;
  873. uint8_t *ecc_pos;
  874. int stat;
  875. /* read the page */
  876. chip->read_buf(mtd, p, eccsize);
  877. /* move to ECC position if needed */
  878. if (eccpos[0] != 0) {
  879. /* This only works on large pages
  880. * because the ECC controller waits for
  881. * NAND_CMD_RNDOUTSTART after the
  882. * NAND_CMD_RNDOUT.
  883. * anyway, for small pages, the eccpos[0] == 0
  884. */
  885. chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
  886. mtd->writesize + eccpos[0], -1);
  887. }
  888. /* the ECC controller needs to read the ECC just after the data */
  889. ecc_pos = oob + eccpos[0];
  890. chip->read_buf(mtd, ecc_pos, eccbytes);
  891. /* check if there's an error */
  892. stat = chip->ecc.correct(mtd, p, oob, NULL);
  893. if (stat < 0)
  894. mtd->ecc_stats.failed++;
  895. else
  896. mtd->ecc_stats.corrected += stat;
  897. /* get back to oob start (end of page) */
  898. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
  899. /* read the oob */
  900. chip->read_buf(mtd, oob, mtd->oobsize);
  901. return 0;
  902. }
  903. /*
  904. * HW ECC Correction
  905. *
  906. * function called after a read
  907. *
  908. * mtd: MTD block structure
  909. * dat: raw data read from the chip
  910. * read_ecc: ECC from the chip (unused)
  911. * isnull: unused
  912. *
  913. * Detect and correct a 1 bit error for a page
  914. */
  915. static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
  916. u_char *read_ecc, u_char *isnull)
  917. {
  918. struct nand_chip *nand_chip = mtd->priv;
  919. unsigned int ecc_status;
  920. unsigned int ecc_word, ecc_bit;
  921. /* get the status from the Status Register */
  922. ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
  923. /* if there's no error */
  924. if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
  925. return 0;
  926. /* get error bit offset (4 bits) */
  927. ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
  928. /* get word address (12 bits) */
  929. ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
  930. ecc_word >>= 4;
  931. /* if there are multiple errors */
  932. if (ecc_status & ATMEL_ECC_MULERR) {
  933. /* check if it is a freshly erased block
  934. * (filled with 0xff) */
  935. if ((ecc_bit == ATMEL_ECC_BITADDR)
  936. && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
  937. /* the block has just been erased, return OK */
  938. return 0;
  939. }
  940. /* it doesn't seems to be a freshly
  941. * erased block.
  942. * We can't correct so many errors */
  943. dev_warn(host->dev, "atmel_nand : multiple errors detected."
  944. " Unable to correct.\n");
  945. return -EIO;
  946. }
  947. /* if there's a single bit error : we can correct it */
  948. if (ecc_status & ATMEL_ECC_ECCERR) {
  949. /* there's nothing much to do here.
  950. * the bit error is on the ECC itself.
  951. */
  952. dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
  953. " Nothing to correct\n");
  954. return 0;
  955. }
  956. dev_warn(host->dev, "atmel_nand : one bit error on data."
  957. " (word offset in the page :"
  958. " 0x%x bit offset : 0x%x)\n",
  959. ecc_word, ecc_bit);
  960. /* correct the error */
  961. if (nand_chip->options & NAND_BUSWIDTH_16) {
  962. /* 16 bits words */
  963. ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
  964. } else {
  965. /* 8 bits words */
  966. dat[ecc_word] ^= (1 << ecc_bit);
  967. }
  968. dev_warn(host->dev, "atmel_nand : error corrected\n");
  969. return 1;
  970. }
  971. /*
  972. * Enable HW ECC : unused on most chips
  973. */
  974. static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
  975. {
  976. }
  977. int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
  978. {
  979. nand->ecc.mode = NAND_ECC_HW;
  980. nand->ecc.calculate = atmel_nand_calculate;
  981. nand->ecc.correct = atmel_nand_correct;
  982. nand->ecc.hwctl = atmel_nand_hwctl;
  983. nand->ecc.read_page = atmel_nand_read_page;
  984. nand->ecc.bytes = 4;
  985. if (nand->ecc.mode == NAND_ECC_HW) {
  986. /* ECC is calculated for the whole page (1 step) */
  987. nand->ecc.size = mtd->writesize;
  988. /* set ECC page size and oob layout */
  989. switch (mtd->writesize) {
  990. case 512:
  991. nand->ecc.layout = &atmel_oobinfo_small;
  992. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  993. ATMEL_ECC_PAGESIZE_528);
  994. break;
  995. case 1024:
  996. nand->ecc.layout = &atmel_oobinfo_large;
  997. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  998. ATMEL_ECC_PAGESIZE_1056);
  999. break;
  1000. case 2048:
  1001. nand->ecc.layout = &atmel_oobinfo_large;
  1002. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  1003. ATMEL_ECC_PAGESIZE_2112);
  1004. break;
  1005. case 4096:
  1006. nand->ecc.layout = &atmel_oobinfo_large;
  1007. ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
  1008. ATMEL_ECC_PAGESIZE_4224);
  1009. break;
  1010. default:
  1011. /* page size not handled by HW ECC */
  1012. /* switching back to soft ECC */
  1013. nand->ecc.mode = NAND_ECC_SOFT;
  1014. nand->ecc.calculate = NULL;
  1015. nand->ecc.correct = NULL;
  1016. nand->ecc.hwctl = NULL;
  1017. nand->ecc.read_page = NULL;
  1018. nand->ecc.postpad = 0;
  1019. nand->ecc.prepad = 0;
  1020. nand->ecc.bytes = 0;
  1021. break;
  1022. }
  1023. }
  1024. return 0;
  1025. }
  1026. #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
  1027. #endif /* CONFIG_ATMEL_NAND_HWECC */
  1028. static void at91_nand_hwcontrol(struct mtd_info *mtd,
  1029. int cmd, unsigned int ctrl)
  1030. {
  1031. struct nand_chip *this = mtd->priv;
  1032. if (ctrl & NAND_CTRL_CHANGE) {
  1033. ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
  1034. IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
  1035. | CONFIG_SYS_NAND_MASK_CLE);
  1036. if (ctrl & NAND_CLE)
  1037. IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
  1038. if (ctrl & NAND_ALE)
  1039. IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
  1040. #ifdef CONFIG_SYS_NAND_ENABLE_PIN
  1041. gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
  1042. #endif
  1043. this->IO_ADDR_W = (void *) IO_ADDR_W;
  1044. }
  1045. if (cmd != NAND_CMD_NONE)
  1046. writeb(cmd, this->IO_ADDR_W);
  1047. }
  1048. #ifdef CONFIG_SYS_NAND_READY_PIN
  1049. static int at91_nand_ready(struct mtd_info *mtd)
  1050. {
  1051. return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
  1052. }
  1053. #endif
  1054. #ifdef CONFIG_SPL_BUILD
  1055. /* The following code is for SPL */
  1056. static struct mtd_info mtd;
  1057. static struct nand_chip nand_chip;
  1058. static int nand_command(int block, int page, uint32_t offs, u8 cmd)
  1059. {
  1060. struct nand_chip *this = mtd.priv;
  1061. int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  1062. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  1063. unsigned int ctrl) = this->cmd_ctrl;
  1064. while (!this->dev_ready(&mtd))
  1065. ;
  1066. if (cmd == NAND_CMD_READOOB) {
  1067. offs += CONFIG_SYS_NAND_PAGE_SIZE;
  1068. cmd = NAND_CMD_READ0;
  1069. }
  1070. hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1071. if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
  1072. offs >>= 1;
  1073. hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1074. hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
  1075. hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
  1076. hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
  1077. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  1078. hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
  1079. #endif
  1080. hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1081. hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1082. hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  1083. while (!this->dev_ready(&mtd))
  1084. ;
  1085. return 0;
  1086. }
  1087. static int nand_is_bad_block(int block)
  1088. {
  1089. struct nand_chip *this = mtd.priv;
  1090. nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
  1091. if (this->options & NAND_BUSWIDTH_16) {
  1092. if (readw(this->IO_ADDR_R) != 0xffff)
  1093. return 1;
  1094. } else {
  1095. if (readb(this->IO_ADDR_R) != 0xff)
  1096. return 1;
  1097. }
  1098. return 0;
  1099. }
  1100. #ifdef CONFIG_SPL_NAND_ECC
  1101. static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
  1102. #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
  1103. CONFIG_SYS_NAND_ECCSIZE)
  1104. #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
  1105. static int nand_read_page(int block, int page, void *dst)
  1106. {
  1107. struct nand_chip *this = mtd.priv;
  1108. u_char ecc_calc[ECCTOTAL];
  1109. u_char ecc_code[ECCTOTAL];
  1110. u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
  1111. int eccsize = CONFIG_SYS_NAND_ECCSIZE;
  1112. int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
  1113. int eccsteps = ECCSTEPS;
  1114. int i;
  1115. uint8_t *p = dst;
  1116. nand_command(block, page, 0, NAND_CMD_READ0);
  1117. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1118. if (this->ecc.mode != NAND_ECC_SOFT)
  1119. this->ecc.hwctl(&mtd, NAND_ECC_READ);
  1120. this->read_buf(&mtd, p, eccsize);
  1121. this->ecc.calculate(&mtd, p, &ecc_calc[i]);
  1122. }
  1123. this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
  1124. for (i = 0; i < ECCTOTAL; i++)
  1125. ecc_code[i] = oob_data[nand_ecc_pos[i]];
  1126. eccsteps = ECCSTEPS;
  1127. p = dst;
  1128. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1129. this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
  1130. return 0;
  1131. }
  1132. int spl_nand_erase_one(int block, int page)
  1133. {
  1134. struct nand_chip *this = mtd.priv;
  1135. void (*hwctrl)(struct mtd_info *mtd, int cmd,
  1136. unsigned int ctrl) = this->cmd_ctrl;
  1137. int page_addr;
  1138. if (nand_chip.select_chip)
  1139. nand_chip.select_chip(&mtd, 0);
  1140. page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
  1141. hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1142. /* Row address */
  1143. hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1144. hwctrl(&mtd, ((page_addr >> 8) & 0xff),
  1145. NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1146. #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
  1147. /* One more address cycle for devices > 128MiB */
  1148. hwctrl(&mtd, (page_addr >> 16) & 0x0f,
  1149. NAND_CTRL_ALE | NAND_CTRL_CHANGE);
  1150. #endif
  1151. hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  1152. while (!this->dev_ready(&mtd))
  1153. ;
  1154. nand_deselect();
  1155. return 0;
  1156. }
  1157. #else
  1158. static int nand_read_page(int block, int page, void *dst)
  1159. {
  1160. struct nand_chip *this = mtd.priv;
  1161. nand_command(block, page, 0, NAND_CMD_READ0);
  1162. atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
  1163. return 0;
  1164. }
  1165. #endif /* CONFIG_SPL_NAND_ECC */
  1166. int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
  1167. {
  1168. unsigned int block, lastblock;
  1169. unsigned int page;
  1170. block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
  1171. lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
  1172. page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
  1173. while (block <= lastblock) {
  1174. if (!nand_is_bad_block(block)) {
  1175. while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
  1176. nand_read_page(block, page, dst);
  1177. dst += CONFIG_SYS_NAND_PAGE_SIZE;
  1178. page++;
  1179. }
  1180. page = 0;
  1181. } else {
  1182. lastblock++;
  1183. }
  1184. block++;
  1185. }
  1186. return 0;
  1187. }
  1188. int at91_nand_wait_ready(struct mtd_info *mtd)
  1189. {
  1190. struct nand_chip *this = mtd->priv;
  1191. udelay(this->chip_delay);
  1192. return 1;
  1193. }
  1194. int board_nand_init(struct nand_chip *nand)
  1195. {
  1196. int ret = 0;
  1197. nand->ecc.mode = NAND_ECC_SOFT;
  1198. #ifdef CONFIG_SYS_NAND_DBW_16
  1199. nand->options = NAND_BUSWIDTH_16;
  1200. nand->read_buf = nand_read_buf16;
  1201. #else
  1202. nand->read_buf = nand_read_buf;
  1203. #endif
  1204. nand->cmd_ctrl = at91_nand_hwcontrol;
  1205. #ifdef CONFIG_SYS_NAND_READY_PIN
  1206. nand->dev_ready = at91_nand_ready;
  1207. #else
  1208. nand->dev_ready = at91_nand_wait_ready;
  1209. #endif
  1210. nand->chip_delay = 20;
  1211. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1212. nand->bbt_options |= NAND_BBT_USE_FLASH;
  1213. #endif
  1214. #ifdef CONFIG_ATMEL_NAND_HWECC
  1215. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  1216. ret = atmel_pmecc_nand_init_params(nand, &mtd);
  1217. #endif
  1218. #endif
  1219. return ret;
  1220. }
  1221. void nand_init(void)
  1222. {
  1223. mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
  1224. mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
  1225. mtd.priv = &nand_chip;
  1226. nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
  1227. nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
  1228. board_nand_init(&nand_chip);
  1229. #ifdef CONFIG_SPL_NAND_ECC
  1230. if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
  1231. nand_chip.ecc.calculate = nand_calculate_ecc;
  1232. nand_chip.ecc.correct = nand_correct_data;
  1233. }
  1234. #endif
  1235. if (nand_chip.select_chip)
  1236. nand_chip.select_chip(&mtd, 0);
  1237. }
  1238. void nand_deselect(void)
  1239. {
  1240. if (nand_chip.select_chip)
  1241. nand_chip.select_chip(&mtd, -1);
  1242. }
  1243. #else
  1244. #ifndef CONFIG_SYS_NAND_BASE_LIST
  1245. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  1246. #endif
  1247. static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
  1248. static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
  1249. int atmel_nand_chip_init(int devnum, ulong base_addr)
  1250. {
  1251. int ret;
  1252. struct mtd_info *mtd = &nand_info[devnum];
  1253. struct nand_chip *nand = &nand_chip[devnum];
  1254. mtd->priv = nand;
  1255. nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
  1256. #ifdef CONFIG_NAND_ECC_BCH
  1257. nand->ecc.mode = NAND_ECC_SOFT_BCH;
  1258. #else
  1259. nand->ecc.mode = NAND_ECC_SOFT;
  1260. #endif
  1261. #ifdef CONFIG_SYS_NAND_DBW_16
  1262. nand->options = NAND_BUSWIDTH_16;
  1263. #endif
  1264. nand->cmd_ctrl = at91_nand_hwcontrol;
  1265. #ifdef CONFIG_SYS_NAND_READY_PIN
  1266. nand->dev_ready = at91_nand_ready;
  1267. #endif
  1268. nand->chip_delay = 75;
  1269. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1270. nand->bbt_options |= NAND_BBT_USE_FLASH;
  1271. #endif
  1272. ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
  1273. if (ret)
  1274. return ret;
  1275. #ifdef CONFIG_ATMEL_NAND_HWECC
  1276. #ifdef CONFIG_ATMEL_NAND_HW_PMECC
  1277. ret = atmel_pmecc_nand_init_params(nand, mtd);
  1278. #else
  1279. ret = atmel_hwecc_nand_init_param(nand, mtd);
  1280. #endif
  1281. if (ret)
  1282. return ret;
  1283. #endif
  1284. ret = nand_scan_tail(mtd);
  1285. if (!ret)
  1286. nand_register(devnum);
  1287. return ret;
  1288. }
  1289. void board_nand_init(void)
  1290. {
  1291. int i;
  1292. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  1293. if (atmel_nand_chip_init(i, base_addr[i]))
  1294. dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
  1295. i);
  1296. }
  1297. #endif /* CONFIG_SPL_BUILD */