xilinx.c 6.1 KB

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  1. /*
  2. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  3. *
  4. * (C) Copyright 2002
  5. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  6. * Keith Outwater, keith_outwater@mvis.com
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. /*
  11. * Xilinx FPGA support
  12. */
  13. #include <common.h>
  14. #include <fpga.h>
  15. #include <virtex2.h>
  16. #include <spartan2.h>
  17. #include <spartan3.h>
  18. #include <zynqpl.h>
  19. /* Local Static Functions */
  20. static int xilinx_validate(xilinx_desc *desc, char *fn);
  21. /* ------------------------------------------------------------------------- */
  22. int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
  23. {
  24. unsigned int length;
  25. unsigned int swapsize;
  26. char buffer[80];
  27. unsigned char *dataptr;
  28. unsigned int i;
  29. const fpga_desc *desc;
  30. xilinx_desc *xdesc;
  31. dataptr = (unsigned char *)fpgadata;
  32. /* Find out fpga_description */
  33. desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
  34. /* Assign xilinx device description */
  35. xdesc = desc->devdesc;
  36. /* skip the first bytes of the bitsteam, their meaning is unknown */
  37. length = (*dataptr << 8) + *(dataptr + 1);
  38. dataptr += 2;
  39. dataptr += length;
  40. /* get design name (identifier, length, string) */
  41. length = (*dataptr << 8) + *(dataptr + 1);
  42. dataptr += 2;
  43. if (*dataptr++ != 0x61) {
  44. debug("%s: Design name id not recognized in bitstream\n",
  45. __func__);
  46. return FPGA_FAIL;
  47. }
  48. length = (*dataptr << 8) + *(dataptr + 1);
  49. dataptr += 2;
  50. for (i = 0; i < length; i++)
  51. buffer[i] = *dataptr++;
  52. printf(" design filename = \"%s\"\n", buffer);
  53. /* get part number (identifier, length, string) */
  54. if (*dataptr++ != 0x62) {
  55. printf("%s: Part number id not recognized in bitstream\n",
  56. __func__);
  57. return FPGA_FAIL;
  58. }
  59. length = (*dataptr << 8) + *(dataptr + 1);
  60. dataptr += 2;
  61. for (i = 0; i < length; i++)
  62. buffer[i] = *dataptr++;
  63. if (xdesc->name) {
  64. i = strncmp(buffer, xdesc->name, strlen(xdesc->name));
  65. if (i) {
  66. printf("%s: Wrong bitstream ID for this device\n",
  67. __func__);
  68. printf("%s: Bitstream ID %s, current device ID %d/%s\n",
  69. __func__, buffer, devnum, xdesc->name);
  70. return FPGA_FAIL;
  71. }
  72. } else {
  73. printf("%s: Please fill correct device ID to xilinx_desc\n",
  74. __func__);
  75. }
  76. printf(" part number = \"%s\"\n", buffer);
  77. /* get date (identifier, length, string) */
  78. if (*dataptr++ != 0x63) {
  79. printf("%s: Date identifier not recognized in bitstream\n",
  80. __func__);
  81. return FPGA_FAIL;
  82. }
  83. length = (*dataptr << 8) + *(dataptr+1);
  84. dataptr += 2;
  85. for (i = 0; i < length; i++)
  86. buffer[i] = *dataptr++;
  87. printf(" date = \"%s\"\n", buffer);
  88. /* get time (identifier, length, string) */
  89. if (*dataptr++ != 0x64) {
  90. printf("%s: Time identifier not recognized in bitstream\n",
  91. __func__);
  92. return FPGA_FAIL;
  93. }
  94. length = (*dataptr << 8) + *(dataptr+1);
  95. dataptr += 2;
  96. for (i = 0; i < length; i++)
  97. buffer[i] = *dataptr++;
  98. printf(" time = \"%s\"\n", buffer);
  99. /* get fpga data length (identifier, length) */
  100. if (*dataptr++ != 0x65) {
  101. printf("%s: Data length id not recognized in bitstream\n",
  102. __func__);
  103. return FPGA_FAIL;
  104. }
  105. swapsize = ((unsigned int) *dataptr << 24) +
  106. ((unsigned int) *(dataptr + 1) << 16) +
  107. ((unsigned int) *(dataptr + 2) << 8) +
  108. ((unsigned int) *(dataptr + 3));
  109. dataptr += 4;
  110. printf(" bytes in bitstream = %d\n", swapsize);
  111. return fpga_load(devnum, dataptr, swapsize);
  112. }
  113. int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
  114. {
  115. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  116. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  117. return FPGA_FAIL;
  118. }
  119. return desc->operations->load(desc, buf, bsize);
  120. }
  121. int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  122. {
  123. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  124. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  125. return FPGA_FAIL;
  126. }
  127. return desc->operations->dump(desc, buf, bsize);
  128. }
  129. int xilinx_info(xilinx_desc *desc)
  130. {
  131. int ret_val = FPGA_FAIL;
  132. if (xilinx_validate (desc, (char *)__FUNCTION__)) {
  133. printf ("Family: \t");
  134. switch (desc->family) {
  135. case xilinx_spartan2:
  136. printf ("Spartan-II\n");
  137. break;
  138. case xilinx_spartan3:
  139. printf ("Spartan-III\n");
  140. break;
  141. case xilinx_virtex2:
  142. printf ("Virtex-II\n");
  143. break;
  144. case xilinx_zynq:
  145. printf("Zynq PL\n");
  146. break;
  147. /* Add new family types here */
  148. default:
  149. printf ("Unknown family type, %d\n", desc->family);
  150. }
  151. printf ("Interface type:\t");
  152. switch (desc->iface) {
  153. case slave_serial:
  154. printf ("Slave Serial\n");
  155. break;
  156. case master_serial: /* Not used */
  157. printf ("Master Serial\n");
  158. break;
  159. case slave_parallel:
  160. printf ("Slave Parallel\n");
  161. break;
  162. case jtag_mode: /* Not used */
  163. printf ("JTAG Mode\n");
  164. break;
  165. case slave_selectmap:
  166. printf ("Slave SelectMap Mode\n");
  167. break;
  168. case master_selectmap:
  169. printf ("Master SelectMap Mode\n");
  170. break;
  171. case devcfg:
  172. printf("Device configuration interface (Zynq)\n");
  173. break;
  174. /* Add new interface types here */
  175. default:
  176. printf ("Unsupported interface type, %d\n", desc->iface);
  177. }
  178. printf ("Device Size: \t%d bytes\n"
  179. "Cookie: \t0x%x (%d)\n",
  180. desc->size, desc->cookie, desc->cookie);
  181. if (desc->name)
  182. printf("Device name: \t%s\n", desc->name);
  183. if (desc->iface_fns) {
  184. printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
  185. desc->operations->info(desc);
  186. } else
  187. printf ("No Device Function Table.\n");
  188. ret_val = FPGA_SUCCESS;
  189. } else {
  190. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  191. }
  192. return ret_val;
  193. }
  194. /* ------------------------------------------------------------------------- */
  195. static int xilinx_validate(xilinx_desc *desc, char *fn)
  196. {
  197. int ret_val = false;
  198. if (desc) {
  199. if ((desc->family > min_xilinx_type) &&
  200. (desc->family < max_xilinx_type)) {
  201. if ((desc->iface > min_xilinx_iface_type) &&
  202. (desc->iface < max_xilinx_iface_type)) {
  203. if (desc->size) {
  204. ret_val = true;
  205. } else
  206. printf ("%s: NULL part size\n", fn);
  207. } else
  208. printf ("%s: Invalid Interface type, %d\n",
  209. fn, desc->iface);
  210. } else
  211. printf ("%s: Invalid family type, %d\n", fn, desc->family);
  212. } else
  213. printf ("%s: NULL descriptor!\n", fn);
  214. return ret_val;
  215. }