ehci-faraday.c 3.5 KB

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  1. /*
  2. * Faraday USB 2.0 EHCI Controller
  3. *
  4. * (C) Copyright 2010 Faraday Technology
  5. * Dante Su <dantesu@faraday-tech.com>
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. #include <common.h>
  10. #include <asm/io.h>
  11. #include <usb.h>
  12. #include <usb/fusbh200.h>
  13. #include <usb/fotg210.h>
  14. #include "ehci.h"
  15. #ifndef CONFIG_USB_EHCI_BASE_LIST
  16. #define CONFIG_USB_EHCI_BASE_LIST { CONFIG_USB_EHCI_BASE }
  17. #endif
  18. union ehci_faraday_regs {
  19. struct fusbh200_regs usb;
  20. struct fotg210_regs otg;
  21. };
  22. static inline int ehci_is_fotg2xx(union ehci_faraday_regs *regs)
  23. {
  24. return !readl(&regs->usb.easstr);
  25. }
  26. /*
  27. * Create the appropriate control structures to manage
  28. * a new EHCI host controller.
  29. */
  30. int ehci_hcd_init(int index, enum usb_init_type init,
  31. struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
  32. {
  33. struct ehci_hccr *hccr;
  34. struct ehci_hcor *hcor;
  35. union ehci_faraday_regs *regs;
  36. uint32_t base_list[] = CONFIG_USB_EHCI_BASE_LIST;
  37. if (index < 0 || index >= ARRAY_SIZE(base_list))
  38. return -1;
  39. regs = (void __iomem *)base_list[index];
  40. hccr = (struct ehci_hccr *)&regs->usb.hccr;
  41. hcor = (struct ehci_hcor *)&regs->usb.hcor;
  42. if (ehci_is_fotg2xx(regs)) {
  43. /* A-device bus reset */
  44. /* ... Power off A-device */
  45. setbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSDROP);
  46. /* ... Drop vbus and bus traffic */
  47. clrbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSREQ);
  48. mdelay(1);
  49. /* ... Power on A-device */
  50. clrbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSDROP);
  51. /* ... Drive vbus and bus traffic */
  52. setbits_le32(&regs->otg.otgcsr, OTGCSR_A_BUSREQ);
  53. mdelay(1);
  54. /* Disable OTG & DEV interrupts, triggered at level-high */
  55. writel(IMR_IRQLH | IMR_OTG | IMR_DEV, &regs->otg.imr);
  56. /* Clear all interrupt status */
  57. writel(ISR_HOST | ISR_OTG | ISR_DEV, &regs->otg.isr);
  58. } else {
  59. /* Interrupt=level-high */
  60. setbits_le32(&regs->usb.bmcsr, BMCSR_IRQLH);
  61. /* VBUS on */
  62. clrbits_le32(&regs->usb.bmcsr, BMCSR_VBUS_OFF);
  63. /* Disable all interrupts */
  64. writel(0x00, &regs->usb.bmier);
  65. writel(0x1f, &regs->usb.bmisr);
  66. }
  67. *ret_hccr = hccr;
  68. *ret_hcor = hcor;
  69. return 0;
  70. }
  71. /*
  72. * Destroy the appropriate control structures corresponding
  73. * the the EHCI host controller.
  74. */
  75. int ehci_hcd_stop(int index)
  76. {
  77. return 0;
  78. }
  79. /*
  80. * This ehci_set_usbmode() overrides the weak function
  81. * in "ehci-hcd.c".
  82. */
  83. void ehci_set_usbmode(struct ehci_ctrl *ctrl)
  84. {
  85. /* nothing needs to be done */
  86. }
  87. /*
  88. * This ehci_get_port_speed() overrides the weak function
  89. * in "ehci-hcd.c".
  90. */
  91. int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
  92. {
  93. int spd, ret = PORTSC_PSPD_HS;
  94. union ehci_faraday_regs *regs;
  95. ret = (void __iomem *)((ulong)ctrl->hcor - 0x10);
  96. if (ehci_is_fotg2xx(regs))
  97. spd = OTGCSR_SPD(readl(&regs->otg.otgcsr));
  98. else
  99. spd = BMCSR_SPD(readl(&regs->usb.bmcsr));
  100. switch (spd) {
  101. case 0: /* full speed */
  102. ret = PORTSC_PSPD_FS;
  103. break;
  104. case 1: /* low speed */
  105. ret = PORTSC_PSPD_LS;
  106. break;
  107. case 2: /* high speed */
  108. ret = PORTSC_PSPD_HS;
  109. break;
  110. default:
  111. printf("ehci-faraday: invalid device speed\n");
  112. break;
  113. }
  114. return ret;
  115. }
  116. /*
  117. * This ehci_get_portsc_register() overrides the weak function
  118. * in "ehci-hcd.c".
  119. */
  120. uint32_t *ehci_get_portsc_register(struct ehci_hcor *hcor, int port)
  121. {
  122. /* Faraday EHCI has one and only one portsc register */
  123. if (port) {
  124. /* Printing the message would cause a scan failure! */
  125. debug("The request port(%d) is not configured\n", port);
  126. return NULL;
  127. }
  128. /* Faraday EHCI PORTSC register offset is 0x20 from hcor */
  129. return (uint32_t *)((uint8_t *)hcor + 0x20);
  130. }