spi_flash_ops.c 8.2 KB

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  1. /*
  2. * SPI flash operations
  3. *
  4. * Copyright (C) 2008 Atmel Corporation
  5. * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  6. * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <common.h>
  11. #include <spi.h>
  12. #include <spi_flash.h>
  13. #include <watchdog.h>
  14. #include "spi_flash_internal.h"
  15. static void spi_flash_addr(u32 addr, u8 *cmd)
  16. {
  17. /* cmd[0] is actual command */
  18. cmd[1] = addr >> 16;
  19. cmd[2] = addr >> 8;
  20. cmd[3] = addr >> 0;
  21. }
  22. int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
  23. {
  24. u8 cmd;
  25. int ret;
  26. cmd = CMD_WRITE_STATUS;
  27. ret = spi_flash_write_common(flash, &cmd, 1, &sr, 1);
  28. if (ret < 0) {
  29. debug("SF: fail to write status register\n");
  30. return ret;
  31. }
  32. return 0;
  33. }
  34. #ifdef CONFIG_SPI_FLASH_BAR
  35. int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
  36. {
  37. u8 cmd;
  38. int ret;
  39. if (flash->bank_curr == bank_sel) {
  40. debug("SF: not require to enable bank%d\n", bank_sel);
  41. return 0;
  42. }
  43. cmd = flash->bank_write_cmd;
  44. ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
  45. if (ret < 0) {
  46. debug("SF: fail to write bank register\n");
  47. return ret;
  48. }
  49. flash->bank_curr = bank_sel;
  50. return 0;
  51. }
  52. #endif
  53. int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
  54. {
  55. struct spi_slave *spi = flash->spi;
  56. unsigned long timebase;
  57. int ret;
  58. u8 status;
  59. u8 check_status = 0x0;
  60. u8 poll_bit = STATUS_WIP;
  61. u8 cmd = flash->poll_cmd;
  62. if (cmd == CMD_FLAG_STATUS) {
  63. poll_bit = STATUS_PEC;
  64. check_status = poll_bit;
  65. }
  66. ret = spi_xfer(spi, 8, &cmd, NULL, SPI_XFER_BEGIN);
  67. if (ret) {
  68. debug("SF: fail to read %s status register\n",
  69. cmd == CMD_READ_STATUS ? "read" : "flag");
  70. return ret;
  71. }
  72. timebase = get_timer(0);
  73. do {
  74. WATCHDOG_RESET();
  75. ret = spi_xfer(spi, 8, NULL, &status, 0);
  76. if (ret)
  77. return -1;
  78. if ((status & poll_bit) == check_status)
  79. break;
  80. } while (get_timer(timebase) < timeout);
  81. spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
  82. if ((status & poll_bit) == check_status)
  83. return 0;
  84. /* Timed out */
  85. debug("SF: time out!\n");
  86. return -1;
  87. }
  88. int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
  89. size_t cmd_len, const void *buf, size_t buf_len)
  90. {
  91. struct spi_slave *spi = flash->spi;
  92. unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
  93. int ret;
  94. if (buf == NULL)
  95. timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
  96. ret = spi_claim_bus(flash->spi);
  97. if (ret) {
  98. debug("SF: unable to claim SPI bus\n");
  99. return ret;
  100. }
  101. ret = spi_flash_cmd_write_enable(flash);
  102. if (ret < 0) {
  103. debug("SF: enabling write failed\n");
  104. return ret;
  105. }
  106. ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
  107. if (ret < 0) {
  108. debug("SF: write cmd failed\n");
  109. return ret;
  110. }
  111. ret = spi_flash_cmd_wait_ready(flash, timeout);
  112. if (ret < 0) {
  113. debug("SF: write %s timed out\n",
  114. timeout == SPI_FLASH_PROG_TIMEOUT ?
  115. "program" : "page erase");
  116. return ret;
  117. }
  118. spi_release_bus(spi);
  119. return ret;
  120. }
  121. int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len)
  122. {
  123. u32 erase_size;
  124. u8 cmd[4];
  125. int ret = -1;
  126. erase_size = flash->sector_size;
  127. if (offset % erase_size || len % erase_size) {
  128. debug("SF: Erase offset/length not multiple of erase size\n");
  129. return -1;
  130. }
  131. if (erase_size == 4096)
  132. cmd[0] = CMD_ERASE_4K;
  133. else
  134. cmd[0] = CMD_ERASE_64K;
  135. while (len) {
  136. #ifdef CONFIG_SPI_FLASH_BAR
  137. u8 bank_sel;
  138. bank_sel = offset / SPI_FLASH_16MB_BOUN;
  139. ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
  140. if (ret) {
  141. debug("SF: fail to set bank%d\n", bank_sel);
  142. return ret;
  143. }
  144. #endif
  145. spi_flash_addr(offset, cmd);
  146. debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
  147. cmd[2], cmd[3], offset);
  148. ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
  149. if (ret < 0) {
  150. debug("SF: erase failed\n");
  151. break;
  152. }
  153. offset += erase_size;
  154. len -= erase_size;
  155. }
  156. return ret;
  157. }
  158. int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset,
  159. size_t len, const void *buf)
  160. {
  161. unsigned long byte_addr, page_size;
  162. size_t chunk_len, actual;
  163. u8 cmd[4];
  164. int ret = -1;
  165. page_size = flash->page_size;
  166. cmd[0] = CMD_PAGE_PROGRAM;
  167. for (actual = 0; actual < len; actual += chunk_len) {
  168. #ifdef CONFIG_SPI_FLASH_BAR
  169. u8 bank_sel;
  170. bank_sel = offset / SPI_FLASH_16MB_BOUN;
  171. ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
  172. if (ret) {
  173. debug("SF: fail to set bank%d\n", bank_sel);
  174. return ret;
  175. }
  176. #endif
  177. byte_addr = offset % page_size;
  178. chunk_len = min(len - actual, page_size - byte_addr);
  179. if (flash->spi->max_write_size)
  180. chunk_len = min(chunk_len, flash->spi->max_write_size);
  181. spi_flash_addr(offset, cmd);
  182. debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
  183. buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
  184. ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
  185. buf + actual, chunk_len);
  186. if (ret < 0) {
  187. debug("SF: write failed\n");
  188. break;
  189. }
  190. offset += chunk_len;
  191. }
  192. return ret;
  193. }
  194. int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
  195. size_t cmd_len, void *data, size_t data_len)
  196. {
  197. struct spi_slave *spi = flash->spi;
  198. int ret;
  199. ret = spi_claim_bus(flash->spi);
  200. if (ret) {
  201. debug("SF: unable to claim SPI bus\n");
  202. return ret;
  203. }
  204. ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
  205. if (ret < 0) {
  206. debug("SF: read cmd failed\n");
  207. return ret;
  208. }
  209. spi_release_bus(spi);
  210. return ret;
  211. }
  212. int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset,
  213. size_t len, void *data)
  214. {
  215. u8 cmd[5], bank_sel = 0;
  216. u32 remain_len, read_len;
  217. int ret = -1;
  218. /* Handle memory-mapped SPI */
  219. if (flash->memory_map) {
  220. memcpy(data, flash->memory_map + offset, len);
  221. return 0;
  222. }
  223. cmd[0] = CMD_READ_ARRAY_FAST;
  224. cmd[4] = 0x00;
  225. while (len) {
  226. #ifdef CONFIG_SPI_FLASH_BAR
  227. bank_sel = offset / SPI_FLASH_16MB_BOUN;
  228. ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
  229. if (ret) {
  230. debug("SF: fail to set bank%d\n", bank_sel);
  231. return ret;
  232. }
  233. #endif
  234. remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1) - offset);
  235. if (len < remain_len)
  236. read_len = len;
  237. else
  238. read_len = remain_len;
  239. spi_flash_addr(offset, cmd);
  240. ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
  241. data, read_len);
  242. if (ret < 0) {
  243. debug("SF: read failed\n");
  244. break;
  245. }
  246. offset += read_len;
  247. len -= read_len;
  248. data += read_len;
  249. }
  250. return ret;
  251. }
  252. #ifdef CONFIG_SPI_FLASH_SST
  253. static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
  254. {
  255. int ret;
  256. u8 cmd[4] = {
  257. CMD_SST_BP,
  258. offset >> 16,
  259. offset >> 8,
  260. offset,
  261. };
  262. debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
  263. spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
  264. ret = spi_flash_cmd_write_enable(flash);
  265. if (ret)
  266. return ret;
  267. ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
  268. if (ret)
  269. return ret;
  270. return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  271. }
  272. int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
  273. const void *buf)
  274. {
  275. size_t actual, cmd_len;
  276. int ret;
  277. u8 cmd[4];
  278. ret = spi_claim_bus(flash->spi);
  279. if (ret) {
  280. debug("SF: Unable to claim SPI bus\n");
  281. return ret;
  282. }
  283. /* If the data is not word aligned, write out leading single byte */
  284. actual = offset % 2;
  285. if (actual) {
  286. ret = sst_byte_write(flash, offset, buf);
  287. if (ret)
  288. goto done;
  289. }
  290. offset += actual;
  291. ret = spi_flash_cmd_write_enable(flash);
  292. if (ret)
  293. goto done;
  294. cmd_len = 4;
  295. cmd[0] = CMD_SST_AAI_WP;
  296. cmd[1] = offset >> 16;
  297. cmd[2] = offset >> 8;
  298. cmd[3] = offset;
  299. for (; actual < len - 1; actual += 2) {
  300. debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
  301. spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
  302. cmd[0], offset);
  303. ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
  304. buf + actual, 2);
  305. if (ret) {
  306. debug("SF: sst word program failed\n");
  307. break;
  308. }
  309. ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
  310. if (ret)
  311. break;
  312. cmd_len = 1;
  313. offset += 2;
  314. }
  315. if (!ret)
  316. ret = spi_flash_cmd_write_disable(flash);
  317. /* If there is a single trailing byte, write it out */
  318. if (!ret && actual != len)
  319. ret = sst_byte_write(flash, offset, buf + actual);
  320. done:
  321. debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
  322. ret ? "failure" : "success", len, offset - actual);
  323. spi_release_bus(flash->spi);
  324. return ret;
  325. }
  326. #endif