serial_pl01x.c 6.2 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  4. *
  5. * (C) Copyright 2004
  6. * ARM Ltd.
  7. * Philippe Robin, <philippe.robin@arm.com>
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  28. #include <common.h>
  29. #include <watchdog.h>
  30. #include <asm/io.h>
  31. #include <serial.h>
  32. #include <linux/compiler.h>
  33. #include "serial_pl01x.h"
  34. /*
  35. * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
  36. * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
  37. * Versatile PB has four UARTs.
  38. */
  39. #define CONSOLE_PORT CONFIG_CONS_INDEX
  40. static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  41. #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  42. static void pl01x_putc (int portnum, char c);
  43. static int pl01x_getc (int portnum);
  44. static int pl01x_tstc (int portnum);
  45. unsigned int baudrate = CONFIG_BAUDRATE;
  46. DECLARE_GLOBAL_DATA_PTR;
  47. static struct pl01x_regs *pl01x_get_regs(int portnum)
  48. {
  49. return (struct pl01x_regs *) port[portnum];
  50. }
  51. #ifdef CONFIG_PL010_SERIAL
  52. static int pl01x_serial_init(void)
  53. {
  54. struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
  55. unsigned int divisor;
  56. /* First, disable everything */
  57. writel(0, &regs->pl010_cr);
  58. /* Set baud rate */
  59. switch (baudrate) {
  60. case 9600:
  61. divisor = UART_PL010_BAUD_9600;
  62. break;
  63. case 19200:
  64. divisor = UART_PL010_BAUD_9600;
  65. break;
  66. case 38400:
  67. divisor = UART_PL010_BAUD_38400;
  68. break;
  69. case 57600:
  70. divisor = UART_PL010_BAUD_57600;
  71. break;
  72. case 115200:
  73. divisor = UART_PL010_BAUD_115200;
  74. break;
  75. default:
  76. divisor = UART_PL010_BAUD_38400;
  77. }
  78. writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
  79. writel(divisor & 0xff, &regs->pl010_lcrl);
  80. /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
  81. writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, &regs->pl010_lcrh);
  82. /* Finally, enable the UART */
  83. writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
  84. return 0;
  85. }
  86. #endif /* CONFIG_PL010_SERIAL */
  87. #ifdef CONFIG_PL011_SERIAL
  88. static int pl01x_serial_init(void)
  89. {
  90. struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
  91. unsigned int temp;
  92. unsigned int divider;
  93. unsigned int remainder;
  94. unsigned int fraction;
  95. unsigned int lcr;
  96. #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
  97. /* Empty RX fifo if necessary */
  98. if (readl(&regs->pl011_cr) & UART_PL011_CR_UARTEN) {
  99. while (!(readl(&regs->fr) & UART_PL01x_FR_RXFE))
  100. readl(&regs->dr);
  101. }
  102. #endif
  103. /* First, disable everything */
  104. writel(0, &regs->pl011_cr);
  105. /*
  106. * Set baud rate
  107. *
  108. * IBRD = UART_CLK / (16 * BAUD_RATE)
  109. * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
  110. */
  111. temp = 16 * baudrate;
  112. divider = CONFIG_PL011_CLOCK / temp;
  113. remainder = CONFIG_PL011_CLOCK % temp;
  114. temp = (8 * remainder) / baudrate;
  115. fraction = (temp >> 1) + (temp & 1);
  116. writel(divider, &regs->pl011_ibrd);
  117. writel(fraction, &regs->pl011_fbrd);
  118. /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
  119. lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
  120. writel(lcr, &regs->pl011_lcrh);
  121. #ifdef CONFIG_PL011_SERIAL_RLCR
  122. {
  123. int i;
  124. /*
  125. * Program receive line control register after waiting
  126. * 10 bus cycles. Delay be writing to readonly register
  127. * 10 times
  128. */
  129. for (i = 0; i < 10; i++)
  130. writel(lcr, &regs->fr);
  131. writel(lcr, &regs->pl011_rlcr);
  132. /* lcrh needs to be set again for change to be effective */
  133. writel(lcr, &regs->pl011_lcrh);
  134. }
  135. #endif
  136. /* Finally, enable the UART */
  137. writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE |
  138. UART_PL011_CR_RTS, &regs->pl011_cr);
  139. return 0;
  140. }
  141. #endif /* CONFIG_PL011_SERIAL */
  142. static void pl01x_serial_putc(const char c)
  143. {
  144. if (c == '\n')
  145. pl01x_putc (CONSOLE_PORT, '\r');
  146. pl01x_putc (CONSOLE_PORT, c);
  147. }
  148. static int pl01x_serial_getc(void)
  149. {
  150. return pl01x_getc (CONSOLE_PORT);
  151. }
  152. static int pl01x_serial_tstc(void)
  153. {
  154. return pl01x_tstc (CONSOLE_PORT);
  155. }
  156. static void pl01x_serial_setbrg(void)
  157. {
  158. struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
  159. baudrate = gd->baudrate;
  160. /*
  161. * Flush FIFO and wait for non-busy before changing baudrate to avoid
  162. * crap in console
  163. */
  164. while (!(readl(&regs->fr) & UART_PL01x_FR_TXFE))
  165. WATCHDOG_RESET();
  166. while (readl(&regs->fr) & UART_PL01x_FR_BUSY)
  167. WATCHDOG_RESET();
  168. serial_init();
  169. }
  170. static void pl01x_putc (int portnum, char c)
  171. {
  172. struct pl01x_regs *regs = pl01x_get_regs(portnum);
  173. /* Wait until there is space in the FIFO */
  174. while (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  175. WATCHDOG_RESET();
  176. /* Send the character */
  177. writel(c, &regs->dr);
  178. }
  179. static int pl01x_getc (int portnum)
  180. {
  181. struct pl01x_regs *regs = pl01x_get_regs(portnum);
  182. unsigned int data;
  183. /* Wait until there is data in the FIFO */
  184. while (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  185. WATCHDOG_RESET();
  186. data = readl(&regs->dr);
  187. /* Check for an error flag */
  188. if (data & 0xFFFFFF00) {
  189. /* Clear the error */
  190. writel(0xFFFFFFFF, &regs->ecr);
  191. return -1;
  192. }
  193. return (int) data;
  194. }
  195. static int pl01x_tstc (int portnum)
  196. {
  197. struct pl01x_regs *regs = pl01x_get_regs(portnum);
  198. WATCHDOG_RESET();
  199. return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  200. }
  201. static struct serial_device pl01x_serial_drv = {
  202. .name = "pl01x_serial",
  203. .start = pl01x_serial_init,
  204. .stop = NULL,
  205. .setbrg = pl01x_serial_setbrg,
  206. .putc = pl01x_serial_putc,
  207. .puts = default_serial_puts,
  208. .getc = pl01x_serial_getc,
  209. .tstc = pl01x_serial_tstc,
  210. };
  211. void pl01x_serial_initialize(void)
  212. {
  213. serial_register(&pl01x_serial_drv);
  214. }
  215. __weak struct serial_device *default_serial_console(void)
  216. {
  217. return &pl01x_serial_drv;
  218. }