asix.c 16 KB

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. * See file CREDITS for list of people who contributed to this
  4. * project.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #include <common.h>
  22. #include <usb.h>
  23. #include <linux/mii.h>
  24. #include "usb_ether.h"
  25. /* ASIX AX8817X based USB 2.0 Ethernet Devices */
  26. #define AX_CMD_SET_SW_MII 0x06
  27. #define AX_CMD_READ_MII_REG 0x07
  28. #define AX_CMD_WRITE_MII_REG 0x08
  29. #define AX_CMD_SET_HW_MII 0x0a
  30. #define AX_CMD_READ_RX_CTL 0x0f
  31. #define AX_CMD_WRITE_RX_CTL 0x10
  32. #define AX_CMD_WRITE_IPG0 0x12
  33. #define AX_CMD_READ_NODE_ID 0x13
  34. #define AX_CMD_READ_PHY_ID 0x19
  35. #define AX_CMD_WRITE_MEDIUM_MODE 0x1b
  36. #define AX_CMD_WRITE_GPIOS 0x1f
  37. #define AX_CMD_SW_RESET 0x20
  38. #define AX_CMD_SW_PHY_SELECT 0x22
  39. #define AX_SWRESET_CLEAR 0x00
  40. #define AX_SWRESET_PRTE 0x04
  41. #define AX_SWRESET_PRL 0x08
  42. #define AX_SWRESET_IPRL 0x20
  43. #define AX_SWRESET_IPPD 0x40
  44. #define AX88772_IPG0_DEFAULT 0x15
  45. #define AX88772_IPG1_DEFAULT 0x0c
  46. #define AX88772_IPG2_DEFAULT 0x12
  47. /* AX88772 & AX88178 Medium Mode Register */
  48. #define AX_MEDIUM_PF 0x0080
  49. #define AX_MEDIUM_JFE 0x0040
  50. #define AX_MEDIUM_TFC 0x0020
  51. #define AX_MEDIUM_RFC 0x0010
  52. #define AX_MEDIUM_ENCK 0x0008
  53. #define AX_MEDIUM_AC 0x0004
  54. #define AX_MEDIUM_FD 0x0002
  55. #define AX_MEDIUM_GM 0x0001
  56. #define AX_MEDIUM_SM 0x1000
  57. #define AX_MEDIUM_SBP 0x0800
  58. #define AX_MEDIUM_PS 0x0200
  59. #define AX_MEDIUM_RE 0x0100
  60. #define AX88178_MEDIUM_DEFAULT \
  61. (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
  62. AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
  63. AX_MEDIUM_RE)
  64. #define AX88772_MEDIUM_DEFAULT \
  65. (AX_MEDIUM_FD | AX_MEDIUM_RFC | \
  66. AX_MEDIUM_TFC | AX_MEDIUM_PS | \
  67. AX_MEDIUM_AC | AX_MEDIUM_RE)
  68. /* AX88772 & AX88178 RX_CTL values */
  69. #define AX_RX_CTL_SO 0x0080
  70. #define AX_RX_CTL_AB 0x0008
  71. #define AX_DEFAULT_RX_CTL \
  72. (AX_RX_CTL_SO | AX_RX_CTL_AB)
  73. /* GPIO 2 toggles */
  74. #define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */
  75. #define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */
  76. #define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */
  77. /* local defines */
  78. #define ASIX_BASE_NAME "asx"
  79. #define USB_CTRL_SET_TIMEOUT 5000
  80. #define USB_CTRL_GET_TIMEOUT 5000
  81. #define USB_BULK_SEND_TIMEOUT 5000
  82. #define USB_BULK_RECV_TIMEOUT 5000
  83. #define AX_RX_URB_SIZE 2048
  84. #define PHY_CONNECT_TIMEOUT 5000
  85. /* local vars */
  86. static int curr_eth_dev; /* index for name of next device detected */
  87. /*
  88. * Asix infrastructure commands
  89. */
  90. static int asix_write_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
  91. u16 size, void *data)
  92. {
  93. int len;
  94. debug("asix_write_cmd() cmd=0x%02x value=0x%04x index=0x%04x "
  95. "size=%d\n", cmd, value, index, size);
  96. len = usb_control_msg(
  97. dev->pusb_dev,
  98. usb_sndctrlpipe(dev->pusb_dev, 0),
  99. cmd,
  100. USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  101. value,
  102. index,
  103. data,
  104. size,
  105. USB_CTRL_SET_TIMEOUT);
  106. return len == size ? 0 : -1;
  107. }
  108. static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index,
  109. u16 size, void *data)
  110. {
  111. int len;
  112. debug("asix_read_cmd() cmd=0x%02x value=0x%04x index=0x%04x size=%d\n",
  113. cmd, value, index, size);
  114. len = usb_control_msg(
  115. dev->pusb_dev,
  116. usb_rcvctrlpipe(dev->pusb_dev, 0),
  117. cmd,
  118. USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  119. value,
  120. index,
  121. data,
  122. size,
  123. USB_CTRL_GET_TIMEOUT);
  124. return len == size ? 0 : -1;
  125. }
  126. static inline int asix_set_sw_mii(struct ueth_data *dev)
  127. {
  128. int ret;
  129. ret = asix_write_cmd(dev, AX_CMD_SET_SW_MII, 0x0000, 0, 0, NULL);
  130. if (ret < 0)
  131. debug("Failed to enable software MII access\n");
  132. return ret;
  133. }
  134. static inline int asix_set_hw_mii(struct ueth_data *dev)
  135. {
  136. int ret;
  137. ret = asix_write_cmd(dev, AX_CMD_SET_HW_MII, 0x0000, 0, 0, NULL);
  138. if (ret < 0)
  139. debug("Failed to enable hardware MII access\n");
  140. return ret;
  141. }
  142. static int asix_mdio_read(struct ueth_data *dev, int phy_id, int loc)
  143. {
  144. __le16 res;
  145. asix_set_sw_mii(dev);
  146. asix_read_cmd(dev, AX_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, &res);
  147. asix_set_hw_mii(dev);
  148. debug("asix_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
  149. phy_id, loc, le16_to_cpu(res));
  150. return le16_to_cpu(res);
  151. }
  152. static void
  153. asix_mdio_write(struct ueth_data *dev, int phy_id, int loc, int val)
  154. {
  155. __le16 res = cpu_to_le16(val);
  156. debug("asix_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
  157. phy_id, loc, val);
  158. asix_set_sw_mii(dev);
  159. asix_write_cmd(dev, AX_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res);
  160. asix_set_hw_mii(dev);
  161. }
  162. /*
  163. * Asix "high level" commands
  164. */
  165. static int asix_sw_reset(struct ueth_data *dev, u8 flags)
  166. {
  167. int ret;
  168. ret = asix_write_cmd(dev, AX_CMD_SW_RESET, flags, 0, 0, NULL);
  169. if (ret < 0)
  170. debug("Failed to send software reset: %02x\n", ret);
  171. else
  172. udelay(150 * 1000);
  173. return ret;
  174. }
  175. static inline int asix_get_phy_addr(struct ueth_data *dev)
  176. {
  177. u8 buf[2];
  178. int ret = asix_read_cmd(dev, AX_CMD_READ_PHY_ID, 0, 0, 2, buf);
  179. debug("asix_get_phy_addr()\n");
  180. if (ret < 0) {
  181. debug("Error reading PHYID register: %02x\n", ret);
  182. goto out;
  183. }
  184. debug("asix_get_phy_addr() returning 0x%02x%02x\n", buf[0], buf[1]);
  185. ret = buf[1];
  186. out:
  187. return ret;
  188. }
  189. static int asix_write_medium_mode(struct ueth_data *dev, u16 mode)
  190. {
  191. int ret;
  192. debug("asix_write_medium_mode() - mode = 0x%04x\n", mode);
  193. ret = asix_write_cmd(dev, AX_CMD_WRITE_MEDIUM_MODE, mode,
  194. 0, 0, NULL);
  195. if (ret < 0) {
  196. debug("Failed to write Medium Mode mode to 0x%04x: %02x\n",
  197. mode, ret);
  198. }
  199. return ret;
  200. }
  201. static u16 asix_read_rx_ctl(struct ueth_data *dev)
  202. {
  203. __le16 v;
  204. int ret = asix_read_cmd(dev, AX_CMD_READ_RX_CTL, 0, 0, 2, &v);
  205. if (ret < 0)
  206. debug("Error reading RX_CTL register: %02x\n", ret);
  207. else
  208. ret = le16_to_cpu(v);
  209. return ret;
  210. }
  211. static int asix_write_rx_ctl(struct ueth_data *dev, u16 mode)
  212. {
  213. int ret;
  214. debug("asix_write_rx_ctl() - mode = 0x%04x\n", mode);
  215. ret = asix_write_cmd(dev, AX_CMD_WRITE_RX_CTL, mode, 0, 0, NULL);
  216. if (ret < 0) {
  217. debug("Failed to write RX_CTL mode to 0x%04x: %02x\n",
  218. mode, ret);
  219. }
  220. return ret;
  221. }
  222. static int asix_write_gpio(struct ueth_data *dev, u16 value, int sleep)
  223. {
  224. int ret;
  225. debug("asix_write_gpio() - value = 0x%04x\n", value);
  226. ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS, value, 0, 0, NULL);
  227. if (ret < 0) {
  228. debug("Failed to write GPIO value 0x%04x: %02x\n",
  229. value, ret);
  230. }
  231. if (sleep)
  232. udelay(sleep * 1000);
  233. return ret;
  234. }
  235. /*
  236. * mii commands
  237. */
  238. /*
  239. * mii_nway_restart - restart NWay (autonegotiation) for this interface
  240. *
  241. * Returns 0 on success, negative on error.
  242. */
  243. static int mii_nway_restart(struct ueth_data *dev)
  244. {
  245. int bmcr;
  246. int r = -1;
  247. /* if autoneg is off, it's an error */
  248. bmcr = asix_mdio_read(dev, dev->phy_id, MII_BMCR);
  249. if (bmcr & BMCR_ANENABLE) {
  250. bmcr |= BMCR_ANRESTART;
  251. asix_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
  252. r = 0;
  253. }
  254. return r;
  255. }
  256. /*
  257. * Asix callbacks
  258. */
  259. static int asix_init(struct eth_device *eth, bd_t *bd)
  260. {
  261. int embd_phy;
  262. unsigned char buf[ETH_ALEN];
  263. u16 rx_ctl;
  264. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  265. int timeout = 0;
  266. #define TIMEOUT_RESOLUTION 50 /* ms */
  267. int link_detected;
  268. debug("** %s()\n", __func__);
  269. if (asix_write_gpio(dev,
  270. AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5) < 0)
  271. goto out_err;
  272. /* 0x10 is the phy id of the embedded 10/100 ethernet phy */
  273. embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
  274. if (asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT,
  275. embd_phy, 0, 0, NULL) < 0) {
  276. debug("Select PHY #1 failed\n");
  277. goto out_err;
  278. }
  279. if (asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL) < 0)
  280. goto out_err;
  281. if (asix_sw_reset(dev, AX_SWRESET_CLEAR) < 0)
  282. goto out_err;
  283. if (embd_phy) {
  284. if (asix_sw_reset(dev, AX_SWRESET_IPRL) < 0)
  285. goto out_err;
  286. } else {
  287. if (asix_sw_reset(dev, AX_SWRESET_PRTE) < 0)
  288. goto out_err;
  289. }
  290. rx_ctl = asix_read_rx_ctl(dev);
  291. debug("RX_CTL is 0x%04x after software reset\n", rx_ctl);
  292. if (asix_write_rx_ctl(dev, 0x0000) < 0)
  293. goto out_err;
  294. rx_ctl = asix_read_rx_ctl(dev);
  295. debug("RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
  296. /* Get the MAC address */
  297. if (asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
  298. 0, 0, ETH_ALEN, buf) < 0) {
  299. debug("Failed to read MAC address.\n");
  300. goto out_err;
  301. }
  302. memcpy(eth->enetaddr, buf, ETH_ALEN);
  303. debug("MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
  304. eth->enetaddr[0], eth->enetaddr[1],
  305. eth->enetaddr[2], eth->enetaddr[3],
  306. eth->enetaddr[4], eth->enetaddr[5]);
  307. dev->phy_id = asix_get_phy_addr(dev);
  308. if (dev->phy_id < 0)
  309. debug("Failed to read phy id\n");
  310. if (asix_sw_reset(dev, AX_SWRESET_PRL) < 0)
  311. goto out_err;
  312. if (asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL) < 0)
  313. goto out_err;
  314. asix_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
  315. asix_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
  316. ADVERTISE_ALL | ADVERTISE_CSMA);
  317. mii_nway_restart(dev);
  318. if (asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT) < 0)
  319. goto out_err;
  320. if (asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
  321. AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
  322. AX88772_IPG2_DEFAULT, 0, NULL) < 0) {
  323. debug("Write IPG,IPG1,IPG2 failed\n");
  324. goto out_err;
  325. }
  326. if (asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL) < 0)
  327. goto out_err;
  328. do {
  329. link_detected = asix_mdio_read(dev, dev->phy_id, MII_BMSR) &
  330. BMSR_LSTATUS;
  331. if (!link_detected) {
  332. if (timeout == 0)
  333. printf("Waiting for Ethernet connection... ");
  334. udelay(TIMEOUT_RESOLUTION * 1000);
  335. timeout += TIMEOUT_RESOLUTION;
  336. }
  337. } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
  338. if (link_detected) {
  339. if (timeout != 0)
  340. printf("done.\n");
  341. } else {
  342. printf("unable to connect.\n");
  343. goto out_err;
  344. }
  345. return 0;
  346. out_err:
  347. return -1;
  348. }
  349. static int asix_send(struct eth_device *eth, volatile void *packet, int length)
  350. {
  351. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  352. int err;
  353. u32 packet_len;
  354. int actual_len;
  355. unsigned char msg[PKTSIZE + sizeof(packet_len)];
  356. debug("** %s(), len %d\n", __func__, length);
  357. packet_len = (((length) ^ 0x0000ffff) << 16) + (length);
  358. cpu_to_le32s(&packet_len);
  359. memcpy(msg, &packet_len, sizeof(packet_len));
  360. memcpy(msg + sizeof(packet_len), (void *)packet, length);
  361. if (length & 1)
  362. length++;
  363. err = usb_bulk_msg(dev->pusb_dev,
  364. usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
  365. (void *)msg,
  366. length + sizeof(packet_len),
  367. &actual_len,
  368. USB_BULK_SEND_TIMEOUT);
  369. debug("Tx: len = %u, actual = %u, err = %d\n",
  370. length + sizeof(packet_len), actual_len, err);
  371. return err;
  372. }
  373. static int asix_recv(struct eth_device *eth)
  374. {
  375. struct ueth_data *dev = (struct ueth_data *)eth->priv;
  376. static unsigned char recv_buf[AX_RX_URB_SIZE];
  377. unsigned char *buf_ptr;
  378. int err;
  379. int actual_len;
  380. u32 packet_len;
  381. debug("** %s()\n", __func__);
  382. err = usb_bulk_msg(dev->pusb_dev,
  383. usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
  384. (void *)recv_buf,
  385. AX_RX_URB_SIZE,
  386. &actual_len,
  387. USB_BULK_RECV_TIMEOUT);
  388. debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
  389. actual_len, err);
  390. if (err != 0) {
  391. debug("Rx: failed to receive\n");
  392. return -1;
  393. }
  394. if (actual_len > AX_RX_URB_SIZE) {
  395. debug("Rx: received too many bytes %d\n", actual_len);
  396. return -1;
  397. }
  398. buf_ptr = recv_buf;
  399. while (actual_len > 0) {
  400. /*
  401. * 1st 4 bytes contain the length of the actual data as two
  402. * complementary 16-bit words. Extract the length of the data.
  403. */
  404. if (actual_len < sizeof(packet_len)) {
  405. debug("Rx: incomplete packet length\n");
  406. return -1;
  407. }
  408. memcpy(&packet_len, buf_ptr, sizeof(packet_len));
  409. le32_to_cpus(&packet_len);
  410. if (((packet_len >> 16) ^ 0xffff) != (packet_len & 0xffff)) {
  411. debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
  412. packet_len, (packet_len >> 16) ^ 0xffff,
  413. packet_len & 0xffff);
  414. return -1;
  415. }
  416. packet_len = packet_len & 0xffff;
  417. if (packet_len > actual_len - sizeof(packet_len)) {
  418. debug("Rx: too large packet: %d\n", packet_len);
  419. return -1;
  420. }
  421. /* Notify net stack */
  422. NetReceive(buf_ptr + sizeof(packet_len), packet_len);
  423. /* Adjust for next iteration. Packets are padded to 16-bits */
  424. if (packet_len & 1)
  425. packet_len++;
  426. actual_len -= sizeof(packet_len) + packet_len;
  427. buf_ptr += sizeof(packet_len) + packet_len;
  428. }
  429. return err;
  430. }
  431. static void asix_halt(struct eth_device *eth)
  432. {
  433. debug("** %s()\n", __func__);
  434. }
  435. /*
  436. * Asix probing functions
  437. */
  438. void asix_eth_before_probe(void)
  439. {
  440. curr_eth_dev = 0;
  441. }
  442. struct asix_dongle {
  443. unsigned short vendor;
  444. unsigned short product;
  445. };
  446. static struct asix_dongle asix_dongles[] = {
  447. { 0x05ac, 0x1402 }, /* Apple USB Ethernet Adapter */
  448. { 0x07d1, 0x3c05 }, /* D-Link DUB-E100 H/W Ver B1 */
  449. { 0x0b95, 0x772a }, /* Cables-to-Go USB Ethernet Adapter */
  450. { 0x0b95, 0x7720 }, /* Trendnet TU2-ET100 V3.0R */
  451. { 0x0b95, 0x1720 }, /* SMC */
  452. { 0x0db0, 0xa877 }, /* MSI - ASIX 88772a */
  453. { 0x13b1, 0x0018 }, /* Linksys 200M v2.1 */
  454. { 0x1557, 0x7720 }, /* 0Q0 cable ethernet */
  455. { 0x2001, 0x3c05 }, /* DLink DUB-E100 H/W Ver B1 Alternate */
  456. { 0x0000, 0x0000 } /* END - Do not remove */
  457. };
  458. /* Probe to see if a new device is actually an asix device */
  459. int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
  460. struct ueth_data *ss)
  461. {
  462. struct usb_interface *iface;
  463. struct usb_interface_descriptor *iface_desc;
  464. int i;
  465. /* let's examine the device now */
  466. iface = &dev->config.if_desc[ifnum];
  467. iface_desc = &dev->config.if_desc[ifnum].desc;
  468. for (i = 0; asix_dongles[i].vendor != 0; i++) {
  469. if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
  470. dev->descriptor.idProduct == asix_dongles[i].product)
  471. /* Found a supported dongle */
  472. break;
  473. }
  474. if (asix_dongles[i].vendor == 0)
  475. return 0;
  476. memset(ss, 0, sizeof(struct ueth_data));
  477. /* At this point, we know we've got a live one */
  478. debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
  479. dev->descriptor.idVendor, dev->descriptor.idProduct);
  480. /* Initialize the ueth_data structure with some useful info */
  481. ss->ifnum = ifnum;
  482. ss->pusb_dev = dev;
  483. ss->subclass = iface_desc->bInterfaceSubClass;
  484. ss->protocol = iface_desc->bInterfaceProtocol;
  485. /*
  486. * We are expecting a minimum of 3 endpoints - in, out (bulk), and
  487. * int. We will ignore any others.
  488. */
  489. for (i = 0; i < iface_desc->bNumEndpoints; i++) {
  490. /* is it an BULK endpoint? */
  491. if ((iface->ep_desc[i].bmAttributes &
  492. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
  493. if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
  494. ss->ep_in = iface->ep_desc[i].bEndpointAddress &
  495. USB_ENDPOINT_NUMBER_MASK;
  496. else
  497. ss->ep_out =
  498. iface->ep_desc[i].bEndpointAddress &
  499. USB_ENDPOINT_NUMBER_MASK;
  500. }
  501. /* is it an interrupt endpoint? */
  502. if ((iface->ep_desc[i].bmAttributes &
  503. USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
  504. ss->ep_int = iface->ep_desc[i].bEndpointAddress &
  505. USB_ENDPOINT_NUMBER_MASK;
  506. ss->irqinterval = iface->ep_desc[i].bInterval;
  507. }
  508. }
  509. debug("Endpoints In %d Out %d Int %d\n",
  510. ss->ep_in, ss->ep_out, ss->ep_int);
  511. /* Do some basic sanity checks, and bail if we find a problem */
  512. if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
  513. !ss->ep_in || !ss->ep_out || !ss->ep_int) {
  514. debug("Problems with device\n");
  515. return 0;
  516. }
  517. dev->privptr = (void *)ss;
  518. return 1;
  519. }
  520. int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
  521. struct eth_device *eth)
  522. {
  523. if (!eth) {
  524. debug("%s: missing parameter.\n", __func__);
  525. return 0;
  526. }
  527. sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
  528. eth->init = asix_init;
  529. eth->send = asix_send;
  530. eth->recv = asix_recv;
  531. eth->halt = asix_halt;
  532. eth->priv = ss;
  533. return 1;
  534. }