spl_board_init.c 4.4 KB

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  1. /*
  2. * Copyright (C) 2015-2016 Socionext Inc.
  3. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <debug_uart.h>
  9. #include <spl.h>
  10. #include "init.h"
  11. #include "micro-support-card.h"
  12. #include "soc-info.h"
  13. struct uniphier_spl_initdata {
  14. unsigned int soc_id;
  15. void (*bcu_init)(const struct uniphier_board_data *bd);
  16. void (*early_clk_init)(void);
  17. int (*dpll_init)(const struct uniphier_board_data *bd);
  18. int (*memconf_init)(const struct uniphier_board_data *bd);
  19. void (*dram_clk_init)(void);
  20. int (*umc_init)(const struct uniphier_board_data *bd);
  21. };
  22. static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
  23. #if defined(CONFIG_ARCH_UNIPHIER_SLD3)
  24. {
  25. .soc_id = UNIPHIER_SLD3_ID,
  26. .bcu_init = uniphier_sld3_bcu_init,
  27. .early_clk_init = uniphier_sld3_early_clk_init,
  28. .dpll_init = uniphier_sld3_dpll_init,
  29. .memconf_init = uniphier_memconf_3ch_no_disbit_init,
  30. .dram_clk_init = uniphier_sld3_dram_clk_init,
  31. .umc_init = uniphier_sld3_umc_init,
  32. },
  33. #endif
  34. #if defined(CONFIG_ARCH_UNIPHIER_LD4)
  35. {
  36. .soc_id = UNIPHIER_LD4_ID,
  37. .bcu_init = uniphier_ld4_bcu_init,
  38. .early_clk_init = uniphier_sld3_early_clk_init,
  39. .dpll_init = uniphier_ld4_dpll_init,
  40. .memconf_init = uniphier_memconf_2ch_init,
  41. .dram_clk_init = uniphier_sld3_dram_clk_init,
  42. .umc_init = uniphier_ld4_umc_init,
  43. },
  44. #endif
  45. #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
  46. {
  47. .soc_id = UNIPHIER_PRO4_ID,
  48. .early_clk_init = uniphier_sld3_early_clk_init,
  49. .dpll_init = uniphier_pro4_dpll_init,
  50. .memconf_init = uniphier_memconf_2ch_init,
  51. .dram_clk_init = uniphier_sld3_dram_clk_init,
  52. .umc_init = uniphier_pro4_umc_init,
  53. },
  54. #endif
  55. #if defined(CONFIG_ARCH_UNIPHIER_SLD8)
  56. {
  57. .soc_id = UNIPHIER_SLD8_ID,
  58. .bcu_init = uniphier_ld4_bcu_init,
  59. .early_clk_init = uniphier_sld3_early_clk_init,
  60. .dpll_init = uniphier_sld8_dpll_init,
  61. .memconf_init = uniphier_memconf_2ch_init,
  62. .dram_clk_init = uniphier_sld3_dram_clk_init,
  63. .umc_init = uniphier_sld8_umc_init,
  64. },
  65. #endif
  66. #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
  67. {
  68. .soc_id = UNIPHIER_PRO5_ID,
  69. .early_clk_init = uniphier_sld3_early_clk_init,
  70. .dpll_init = uniphier_pro5_dpll_init,
  71. .memconf_init = uniphier_memconf_2ch_init,
  72. .dram_clk_init = uniphier_pro5_dram_clk_init,
  73. .umc_init = uniphier_pro5_umc_init,
  74. },
  75. #endif
  76. #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
  77. {
  78. .soc_id = UNIPHIER_PXS2_ID,
  79. .early_clk_init = uniphier_sld3_early_clk_init,
  80. .dpll_init = uniphier_pxs2_dpll_init,
  81. .memconf_init = uniphier_memconf_3ch_init,
  82. .dram_clk_init = uniphier_pxs2_dram_clk_init,
  83. .umc_init = uniphier_pxs2_umc_init,
  84. },
  85. #endif
  86. #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
  87. {
  88. .soc_id = UNIPHIER_LD6B_ID,
  89. .early_clk_init = uniphier_sld3_early_clk_init,
  90. .dpll_init = uniphier_pxs2_dpll_init,
  91. .memconf_init = uniphier_memconf_3ch_init,
  92. .dram_clk_init = uniphier_pxs2_dram_clk_init,
  93. .umc_init = uniphier_pxs2_umc_init,
  94. },
  95. #endif
  96. #if defined(CONFIG_ARCH_UNIPHIER_LD11)
  97. {
  98. .soc_id = UNIPHIER_LD11_ID,
  99. .early_clk_init = uniphier_ld11_early_clk_init,
  100. .dpll_init = uniphier_ld11_dpll_init,
  101. .memconf_init = uniphier_memconf_2ch_init,
  102. .dram_clk_init = uniphier_ld11_dram_clk_init,
  103. .umc_init = uniphier_ld11_umc_init,
  104. },
  105. #endif
  106. #if defined(CONFIG_ARCH_UNIPHIER_LD20)
  107. {
  108. .soc_id = UNIPHIER_LD20_ID,
  109. .early_clk_init = uniphier_ld11_early_clk_init,
  110. .dpll_init = uniphier_ld20_dpll_init,
  111. .memconf_init = uniphier_memconf_3ch_init,
  112. .dram_clk_init = uniphier_ld20_dram_clk_init,
  113. .umc_init = uniphier_ld20_umc_init,
  114. },
  115. #endif
  116. };
  117. UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_spl_initdata, uniphier_spl_initdata)
  118. void spl_board_init(void)
  119. {
  120. const struct uniphier_board_data *bd;
  121. const struct uniphier_spl_initdata *initdata;
  122. int ret;
  123. #ifdef CONFIG_DEBUG_UART
  124. debug_uart_init();
  125. #endif
  126. bd = uniphier_get_board_param();
  127. if (!bd)
  128. hang();
  129. initdata = uniphier_get_spl_initdata();
  130. if (!initdata)
  131. hang();
  132. if (initdata->bcu_init)
  133. initdata->bcu_init(bd);
  134. initdata->early_clk_init();
  135. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  136. preloader_console_init();
  137. #endif
  138. ret = initdata->dpll_init(bd);
  139. if (ret) {
  140. pr_err("failed to init DPLL\n");
  141. hang();
  142. }
  143. ret = initdata->memconf_init(bd);
  144. if (ret) {
  145. pr_err("failed to init MEMCONF\n");
  146. hang();
  147. }
  148. initdata->dram_clk_init();
  149. ret = initdata->umc_init(bd);
  150. if (ret) {
  151. pr_err("failed to init DRAM\n");
  152. hang();
  153. }
  154. #ifdef CONFIG_ARM64
  155. dcache_disable();
  156. #endif
  157. }