sdhci-cadence.c 4.5 KB

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  1. /*
  2. * Copyright (C) 2016 Socionext Inc.
  3. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <linux/io.h>
  9. #include <linux/iopoll.h>
  10. #include <linux/sizes.h>
  11. #include <dm/device.h>
  12. #include <libfdt.h>
  13. #include <mmc.h>
  14. #include <sdhci.h>
  15. /* HRS - Host Register Set (specific to Cadence) */
  16. #define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
  17. #define SDHCI_CDNS_HRS04_ACK BIT(26)
  18. #define SDHCI_CDNS_HRS04_RD BIT(25)
  19. #define SDHCI_CDNS_HRS04_WR BIT(24)
  20. #define SDHCI_CDNS_HRS04_RDATA_SHIFT 16
  21. #define SDHCI_CDNS_HRS04_WDATA_SHIFT 8
  22. #define SDHCI_CDNS_HRS04_ADDR_SHIFT 0
  23. /* SRS - Slot Register Set (SDHCI-compatible) */
  24. #define SDHCI_CDNS_SRS_BASE 0x200
  25. /* PHY */
  26. #define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
  27. #define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
  28. #define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
  29. #define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
  30. #define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
  31. #define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
  32. #define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
  33. #define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
  34. #define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
  35. #define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
  36. #define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
  37. #define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
  38. struct sdhci_cdns_plat {
  39. struct mmc_config cfg;
  40. struct mmc mmc;
  41. void __iomem *hrs_addr;
  42. };
  43. struct sdhci_cdns_phy_cfg {
  44. const char *property;
  45. u8 addr;
  46. };
  47. static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
  48. { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
  49. { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
  50. { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
  51. { "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
  52. { "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
  53. { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
  54. { "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
  55. { "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
  56. { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
  57. { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
  58. { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
  59. };
  60. static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat,
  61. u8 addr, u8 data)
  62. {
  63. void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS04;
  64. u32 tmp;
  65. int ret;
  66. tmp = (data << SDHCI_CDNS_HRS04_WDATA_SHIFT) |
  67. (addr << SDHCI_CDNS_HRS04_ADDR_SHIFT);
  68. writel(tmp, reg);
  69. tmp |= SDHCI_CDNS_HRS04_WR;
  70. writel(tmp, reg);
  71. ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 10);
  72. if (ret)
  73. return ret;
  74. tmp &= ~SDHCI_CDNS_HRS04_WR;
  75. writel(tmp, reg);
  76. return 0;
  77. }
  78. static int sdhci_cdns_phy_init(struct sdhci_cdns_plat *plat,
  79. const void *fdt, int nodeoffset)
  80. {
  81. const u32 *prop;
  82. int ret, i;
  83. for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
  84. prop = fdt_getprop(fdt, nodeoffset,
  85. sdhci_cdns_phy_cfgs[i].property, NULL);
  86. if (!prop)
  87. continue;
  88. ret = sdhci_cdns_write_phy_reg(plat,
  89. sdhci_cdns_phy_cfgs[i].addr,
  90. fdt32_to_cpu(*prop));
  91. if (ret)
  92. return ret;
  93. }
  94. return 0;
  95. }
  96. static int sdhci_cdns_bind(struct udevice *dev)
  97. {
  98. struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
  99. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  100. }
  101. static int sdhci_cdns_probe(struct udevice *dev)
  102. {
  103. DECLARE_GLOBAL_DATA_PTR;
  104. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  105. struct sdhci_cdns_plat *plat = dev_get_platdata(dev);
  106. struct sdhci_host *host = dev_get_priv(dev);
  107. fdt_addr_t base;
  108. int ret;
  109. base = dev_get_addr(dev);
  110. if (base == FDT_ADDR_T_NONE)
  111. return -EINVAL;
  112. plat->hrs_addr = devm_ioremap(dev, base, SZ_1K);
  113. if (!plat->hrs_addr)
  114. return -ENOMEM;
  115. host->name = dev->name;
  116. host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE;
  117. host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD;
  118. ret = sdhci_cdns_phy_init(plat, gd->fdt_blob, dev->of_offset);
  119. if (ret)
  120. return ret;
  121. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
  122. if (ret)
  123. return ret;
  124. upriv->mmc = &plat->mmc;
  125. host->mmc = &plat->mmc;
  126. host->mmc->priv = host;
  127. return sdhci_probe(dev);
  128. }
  129. static const struct udevice_id sdhci_cdns_match[] = {
  130. { .compatible = "socionext,uniphier-sd4hc" },
  131. { .compatible = "cdns,sd4hc" },
  132. { /* sentinel */ }
  133. };
  134. U_BOOT_DRIVER(sdhci_cdns) = {
  135. .name = "sdhci-cdns",
  136. .id = UCLASS_MMC,
  137. .of_match = sdhci_cdns_match,
  138. .bind = sdhci_cdns_bind,
  139. .probe = sdhci_cdns_probe,
  140. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  141. .platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat),
  142. .ops = &sdhci_ops,
  143. };