ldpaa_eth.h 4.2 KB

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  1. /*
  2. * Copyright (C) 2014 Freescale Semiconductor
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __LDPAA_ETH_H
  7. #define __LDPAA_ETH_H
  8. #include <linux/netdevice.h>
  9. #include <fsl-mc/fsl_mc.h>
  10. #include <fsl-mc/fsl_dpaa_fd.h>
  11. #include <fsl-mc/fsl_dprc.h>
  12. #include <fsl-mc/fsl_dpni.h>
  13. #include <fsl-mc/fsl_dpbp.h>
  14. #include <fsl-mc/fsl_dpio.h>
  15. #include <fsl-mc/fsl_qbman_portal.h>
  16. #include <fsl-mc/fsl_mc_private.h>
  17. enum ldpaa_eth_type {
  18. LDPAA_ETH_1G_E,
  19. LDPAA_ETH_10G_E,
  20. };
  21. /* Arbitrary values for now, but we'll need to tune */
  22. #define LDPAA_ETH_NUM_BUFS (2 * 7)
  23. #define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2)
  24. #define LDPAA_ETH_RX_BUFFER_SIZE 2048
  25. /* Hardware requires alignment for ingress/egress buffer addresses
  26. * and ingress buffer lengths.
  27. */
  28. #define LDPAA_ETH_BUF_ALIGN 64
  29. /* So far we're only accomodating a skb backpointer in the frame's
  30. * software annotation, but the hardware options are either 0 or 64.
  31. */
  32. #define LDPAA_ETH_SWA_SIZE 64
  33. /* Annotation valid bits in FD FRC */
  34. #define LDPAA_FD_FRC_FASV 0x8000
  35. #define LDPAA_FD_FRC_FAEADV 0x4000
  36. #define LDPAA_FD_FRC_FAPRV 0x2000
  37. #define LDPAA_FD_FRC_FAIADV 0x1000
  38. #define LDPAA_FD_FRC_FASWOV 0x0800
  39. #define LDPAA_FD_FRC_FAICFDV 0x0400
  40. /* Annotation bits in FD CTRL */
  41. #define LDPAA_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */
  42. #define LDPAA_FD_CTRL_PTA 0x00800000
  43. #define LDPAA_FD_CTRL_PTV1 0x00400000
  44. /* TODO: we may want to move this and other WRIOP related defines
  45. * to a separate header
  46. */
  47. /* Frame annotation status */
  48. struct ldpaa_fas {
  49. u8 reserved;
  50. u8 ppid;
  51. __le16 ifpid;
  52. __le32 status;
  53. } __packed;
  54. /* Debug frame, otherwise supposed to be discarded */
  55. #define LDPAA_ETH_FAS_DISC 0x80000000
  56. /* MACSEC frame */
  57. #define LDPAA_ETH_FAS_MS 0x40000000
  58. #define LDPAA_ETH_FAS_PTP 0x08000000
  59. /* Ethernet multicast frame */
  60. #define LDPAA_ETH_FAS_MC 0x04000000
  61. /* Ethernet broadcast frame */
  62. #define LDPAA_ETH_FAS_BC 0x02000000
  63. #define LDPAA_ETH_FAS_KSE 0x00040000
  64. #define LDPAA_ETH_FAS_EOFHE 0x00020000
  65. #define LDPAA_ETH_FAS_MNLE 0x00010000
  66. #define LDPAA_ETH_FAS_TIDE 0x00008000
  67. #define LDPAA_ETH_FAS_PIEE 0x00004000
  68. /* Frame length error */
  69. #define LDPAA_ETH_FAS_FLE 0x00002000
  70. /* Frame physical error; our favourite pastime */
  71. #define LDPAA_ETH_FAS_FPE 0x00001000
  72. #define LDPAA_ETH_FAS_PTE 0x00000080
  73. #define LDPAA_ETH_FAS_ISP 0x00000040
  74. #define LDPAA_ETH_FAS_PHE 0x00000020
  75. #define LDPAA_ETH_FAS_BLE 0x00000010
  76. /* L3 csum validation performed */
  77. #define LDPAA_ETH_FAS_L3CV 0x00000008
  78. /* L3 csum error */
  79. #define LDPAA_ETH_FAS_L3CE 0x00000004
  80. /* L4 csum validation performed */
  81. #define LDPAA_ETH_FAS_L4CV 0x00000002
  82. /* L4 csum error */
  83. #define LDPAA_ETH_FAS_L4CE 0x00000001
  84. /* These bits always signal errors */
  85. #define LDPAA_ETH_RX_ERR_MASK (LDPAA_ETH_FAS_DISC | \
  86. LDPAA_ETH_FAS_KSE | \
  87. LDPAA_ETH_FAS_EOFHE | \
  88. LDPAA_ETH_FAS_MNLE | \
  89. LDPAA_ETH_FAS_TIDE | \
  90. LDPAA_ETH_FAS_PIEE | \
  91. LDPAA_ETH_FAS_FLE | \
  92. LDPAA_ETH_FAS_FPE | \
  93. LDPAA_ETH_FAS_PTE | \
  94. LDPAA_ETH_FAS_ISP | \
  95. LDPAA_ETH_FAS_PHE | \
  96. LDPAA_ETH_FAS_BLE | \
  97. LDPAA_ETH_FAS_L3CE | \
  98. LDPAA_ETH_FAS_L4CE)
  99. /* Unsupported features in the ingress */
  100. #define LDPAA_ETH_RX_UNSUPP_MASK LDPAA_ETH_FAS_MS
  101. /* TODO trim down the bitmask; not all of them apply to Tx-confirm */
  102. #define LDPAA_ETH_TXCONF_ERR_MASK (LDPAA_ETH_FAS_KSE | \
  103. LDPAA_ETH_FAS_EOFHE | \
  104. LDPAA_ETH_FAS_MNLE | \
  105. LDPAA_ETH_FAS_TIDE)
  106. struct ldpaa_eth_priv {
  107. struct eth_device *net_dev;
  108. int dpni_id;
  109. uint16_t dpni_handle;
  110. struct dpni_attr dpni_attrs;
  111. /* Insofar as the MC is concerned, we're using one layout on all 3 types
  112. * of buffers (Rx, Tx, Tx-Conf).
  113. */
  114. struct dpni_buffer_layout buf_layout;
  115. uint16_t tx_data_offset;
  116. uint32_t rx_dflt_fqid;
  117. uint16_t tx_qdid;
  118. uint16_t tx_flow_id;
  119. enum ldpaa_eth_type type; /* 1G or 10G ethernet */
  120. struct phy_device *phydev;
  121. };
  122. extern struct fsl_mc_io *dflt_mc_io;
  123. extern struct fsl_dpbp_obj *dflt_dpbp;
  124. extern struct fsl_dpio_obj *dflt_dpio;
  125. static void ldpaa_dpbp_drain_cnt(int count);
  126. static void ldpaa_dpbp_drain(void);
  127. static int ldpaa_dpbp_seed(uint16_t bpid);
  128. static void ldpaa_dpbp_free(void);
  129. static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv);
  130. static int ldpaa_dpbp_setup(void);
  131. static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv);
  132. #endif /* __LDPAA_H */