clk-uniphier-core.c 8.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016-2017 Socionext Inc.
  4. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <linux/bitops.h>
  10. #include <linux/io.h>
  11. #include <linux/sizes.h>
  12. #include "clk-uniphier.h"
  13. /**
  14. * struct uniphier_clk_priv - private data for UniPhier clock driver
  15. *
  16. * @base: base address of the clock provider
  17. * @data: SoC specific data
  18. */
  19. struct uniphier_clk_priv {
  20. struct udevice *dev;
  21. void __iomem *base;
  22. const struct uniphier_clk_data *data;
  23. };
  24. static void uniphier_clk_gate_enable(struct uniphier_clk_priv *priv,
  25. const struct uniphier_clk_gate_data *gate)
  26. {
  27. u32 val;
  28. val = readl(priv->base + gate->reg);
  29. val |= BIT(gate->bit);
  30. writel(val, priv->base + gate->reg);
  31. }
  32. static void uniphier_clk_mux_set_parent(struct uniphier_clk_priv *priv,
  33. const struct uniphier_clk_mux_data *mux,
  34. u8 id)
  35. {
  36. u32 val;
  37. int i;
  38. for (i = 0; i < mux->num_parents; i++) {
  39. if (mux->parent_ids[i] != id)
  40. continue;
  41. val = readl(priv->base + mux->reg);
  42. val &= ~mux->masks[i];
  43. val |= mux->vals[i];
  44. writel(val, priv->base + mux->reg);
  45. return;
  46. }
  47. WARN_ON(1);
  48. }
  49. static u8 uniphier_clk_mux_get_parent(struct uniphier_clk_priv *priv,
  50. const struct uniphier_clk_mux_data *mux)
  51. {
  52. u32 val;
  53. int i;
  54. val = readl(priv->base + mux->reg);
  55. for (i = 0; i < mux->num_parents; i++)
  56. if ((mux->masks[i] & val) == mux->vals[i])
  57. return mux->parent_ids[i];
  58. dev_err(priv->dev, "invalid mux setting\n");
  59. return UNIPHIER_CLK_ID_INVALID;
  60. }
  61. static const struct uniphier_clk_data *uniphier_clk_get_data(
  62. struct uniphier_clk_priv *priv, u8 id)
  63. {
  64. const struct uniphier_clk_data *data;
  65. for (data = priv->data; data->type != UNIPHIER_CLK_TYPE_END; data++)
  66. if (data->id == id)
  67. return data;
  68. dev_err(priv->dev, "id=%u not found\n", id);
  69. return NULL;
  70. }
  71. static const struct uniphier_clk_data *uniphier_clk_get_parent_data(
  72. struct uniphier_clk_priv *priv,
  73. const struct uniphier_clk_data *data)
  74. {
  75. const struct uniphier_clk_data *parent_data;
  76. u8 parent_id = UNIPHIER_CLK_ID_INVALID;
  77. switch (data->type) {
  78. case UNIPHIER_CLK_TYPE_GATE:
  79. parent_id = data->data.gate.parent_id;
  80. break;
  81. case UNIPHIER_CLK_TYPE_MUX:
  82. parent_id = uniphier_clk_mux_get_parent(priv, &data->data.mux);
  83. break;
  84. default:
  85. break;
  86. }
  87. if (parent_id == UNIPHIER_CLK_ID_INVALID)
  88. return NULL;
  89. parent_data = uniphier_clk_get_data(priv, parent_id);
  90. WARN_ON(!parent_data);
  91. return parent_data;
  92. }
  93. static void __uniphier_clk_enable(struct uniphier_clk_priv *priv,
  94. const struct uniphier_clk_data *data)
  95. {
  96. const struct uniphier_clk_data *parent_data;
  97. if (data->type == UNIPHIER_CLK_TYPE_GATE)
  98. uniphier_clk_gate_enable(priv, &data->data.gate);
  99. parent_data = uniphier_clk_get_parent_data(priv, data);
  100. if (!parent_data)
  101. return;
  102. return __uniphier_clk_enable(priv, parent_data);
  103. }
  104. static int uniphier_clk_enable(struct clk *clk)
  105. {
  106. struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
  107. const struct uniphier_clk_data *data;
  108. data = uniphier_clk_get_data(priv, clk->id);
  109. if (!data)
  110. return -ENODEV;
  111. __uniphier_clk_enable(priv, data);
  112. return 0;
  113. }
  114. static unsigned long __uniphier_clk_get_rate(
  115. struct uniphier_clk_priv *priv,
  116. const struct uniphier_clk_data *data)
  117. {
  118. const struct uniphier_clk_data *parent_data;
  119. if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
  120. return data->data.rate.fixed_rate;
  121. parent_data = uniphier_clk_get_parent_data(priv, data);
  122. if (!parent_data)
  123. return 0;
  124. return __uniphier_clk_get_rate(priv, parent_data);
  125. }
  126. static unsigned long uniphier_clk_get_rate(struct clk *clk)
  127. {
  128. struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
  129. const struct uniphier_clk_data *data;
  130. data = uniphier_clk_get_data(priv, clk->id);
  131. if (!data)
  132. return -ENODEV;
  133. return __uniphier_clk_get_rate(priv, data);
  134. }
  135. static unsigned long __uniphier_clk_set_rate(
  136. struct uniphier_clk_priv *priv,
  137. const struct uniphier_clk_data *data,
  138. unsigned long rate, bool set)
  139. {
  140. const struct uniphier_clk_data *best_parent_data = NULL;
  141. const struct uniphier_clk_data *parent_data;
  142. unsigned long best_rate = 0;
  143. unsigned long parent_rate;
  144. u8 parent_id;
  145. int i;
  146. if (data->type == UNIPHIER_CLK_TYPE_FIXED_RATE)
  147. return data->data.rate.fixed_rate;
  148. if (data->type == UNIPHIER_CLK_TYPE_GATE) {
  149. parent_data = uniphier_clk_get_parent_data(priv, data);
  150. if (!parent_data)
  151. return 0;
  152. return __uniphier_clk_set_rate(priv, parent_data, rate, set);
  153. }
  154. if (WARN_ON(data->type != UNIPHIER_CLK_TYPE_MUX))
  155. return -EINVAL;
  156. for (i = 0; i < data->data.mux.num_parents; i++) {
  157. parent_id = data->data.mux.parent_ids[i];
  158. parent_data = uniphier_clk_get_data(priv, parent_id);
  159. if (WARN_ON(!parent_data))
  160. return -EINVAL;
  161. parent_rate = __uniphier_clk_set_rate(priv, parent_data, rate,
  162. false);
  163. if (parent_rate <= rate && best_rate < parent_rate) {
  164. best_rate = parent_rate;
  165. best_parent_data = parent_data;
  166. }
  167. }
  168. dev_dbg(priv->dev, "id=%u, best_rate=%lu\n", data->id, best_rate);
  169. if (!best_parent_data)
  170. return -EINVAL;
  171. if (!set)
  172. return best_rate;
  173. uniphier_clk_mux_set_parent(priv, &data->data.mux,
  174. best_parent_data->id);
  175. return best_rate = __uniphier_clk_set_rate(priv, best_parent_data,
  176. rate, true);
  177. }
  178. static unsigned long uniphier_clk_set_rate(struct clk *clk, ulong rate)
  179. {
  180. struct uniphier_clk_priv *priv = dev_get_priv(clk->dev);
  181. const struct uniphier_clk_data *data;
  182. data = uniphier_clk_get_data(priv, clk->id);
  183. if (!data)
  184. return -ENODEV;
  185. return __uniphier_clk_set_rate(priv, data, rate, true);
  186. }
  187. static const struct clk_ops uniphier_clk_ops = {
  188. .enable = uniphier_clk_enable,
  189. .get_rate = uniphier_clk_get_rate,
  190. .set_rate = uniphier_clk_set_rate,
  191. };
  192. static int uniphier_clk_probe(struct udevice *dev)
  193. {
  194. struct uniphier_clk_priv *priv = dev_get_priv(dev);
  195. fdt_addr_t addr;
  196. addr = devfdt_get_addr(dev->parent);
  197. if (addr == FDT_ADDR_T_NONE)
  198. return -EINVAL;
  199. priv->base = devm_ioremap(dev, addr, SZ_4K);
  200. if (!priv->base)
  201. return -ENOMEM;
  202. priv->dev = dev;
  203. priv->data = (void *)dev_get_driver_data(dev);
  204. return 0;
  205. }
  206. static const struct udevice_id uniphier_clk_match[] = {
  207. /* System clock */
  208. {
  209. .compatible = "socionext,uniphier-ld4-clock",
  210. .data = (ulong)uniphier_pxs2_sys_clk_data,
  211. },
  212. {
  213. .compatible = "socionext,uniphier-pro4-clock",
  214. .data = (ulong)uniphier_pxs2_sys_clk_data,
  215. },
  216. {
  217. .compatible = "socionext,uniphier-sld8-clock",
  218. .data = (ulong)uniphier_pxs2_sys_clk_data,
  219. },
  220. {
  221. .compatible = "socionext,uniphier-pro5-clock",
  222. .data = (ulong)uniphier_pxs2_sys_clk_data,
  223. },
  224. {
  225. .compatible = "socionext,uniphier-pxs2-clock",
  226. .data = (ulong)uniphier_pxs2_sys_clk_data,
  227. },
  228. {
  229. .compatible = "socionext,uniphier-ld11-clock",
  230. .data = (ulong)uniphier_ld20_sys_clk_data,
  231. },
  232. {
  233. .compatible = "socionext,uniphier-ld20-clock",
  234. .data = (ulong)uniphier_ld20_sys_clk_data,
  235. },
  236. {
  237. .compatible = "socionext,uniphier-pxs3-clock",
  238. .data = (ulong)uniphier_pxs3_sys_clk_data,
  239. },
  240. /* Media I/O clock */
  241. {
  242. .compatible = "socionext,uniphier-ld4-mio-clock",
  243. .data = (ulong)uniphier_mio_clk_data,
  244. },
  245. {
  246. .compatible = "socionext,uniphier-pro4-mio-clock",
  247. .data = (ulong)uniphier_mio_clk_data,
  248. },
  249. {
  250. .compatible = "socionext,uniphier-sld8-mio-clock",
  251. .data = (ulong)uniphier_mio_clk_data,
  252. },
  253. {
  254. .compatible = "socionext,uniphier-pro5-sd-clock",
  255. .data = (ulong)uniphier_mio_clk_data,
  256. },
  257. {
  258. .compatible = "socionext,uniphier-pxs2-sd-clock",
  259. .data = (ulong)uniphier_mio_clk_data,
  260. },
  261. {
  262. .compatible = "socionext,uniphier-ld11-mio-clock",
  263. .data = (ulong)uniphier_mio_clk_data,
  264. },
  265. {
  266. .compatible = "socionext,uniphier-ld20-sd-clock",
  267. .data = (ulong)uniphier_mio_clk_data,
  268. },
  269. {
  270. .compatible = "socionext,uniphier-pxs3-sd-clock",
  271. .data = (ulong)uniphier_mio_clk_data,
  272. },
  273. { /* sentinel */ }
  274. };
  275. U_BOOT_DRIVER(uniphier_clk) = {
  276. .name = "uniphier-clk",
  277. .id = UCLASS_CLK,
  278. .of_match = uniphier_clk_match,
  279. .probe = uniphier_clk_probe,
  280. .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv),
  281. .ops = &uniphier_clk_ops,
  282. };