chromebox_panther.dts 1.6 KB

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  1. /dts-v1/;
  2. /include/ "skeleton.dtsi"
  3. /include/ "serial.dtsi"
  4. /include/ "reset.dtsi"
  5. /include/ "rtc.dtsi"
  6. /include/ "tsc_timer.dtsi"
  7. /include/ "coreboot_fb.dtsi"
  8. / {
  9. model = "Google Panther";
  10. compatible = "google,panther", "intel,haswell";
  11. aliases {
  12. spi0 = &spi;
  13. };
  14. config {
  15. silent-console = <0>;
  16. no-keyboard;
  17. };
  18. chosen {
  19. stdout-path = "/serial";
  20. };
  21. pci {
  22. compatible = "pci-x86";
  23. #address-cells = <3>;
  24. #size-cells = <2>;
  25. u-boot,dm-pre-reloc;
  26. ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  27. 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  28. 0x01000000 0x0 0x1000 0x1000 0 0xf000>;
  29. pch@1f,0 {
  30. reg = <0x0000f800 0 0 0 0>;
  31. compatible = "intel,pch9";
  32. #address-cells = <1>;
  33. #size-cells = <1>;
  34. spi: spi {
  35. #address-cells = <1>;
  36. #size-cells = <0>;
  37. compatible = "intel,ich9-spi";
  38. spi-flash@0 {
  39. #size-cells = <1>;
  40. #address-cells = <1>;
  41. reg = <0>;
  42. compatible = "winbond,w25q64",
  43. "spi-flash";
  44. memory-map = <0xff800000 0x00800000>;
  45. rw-mrc-cache {
  46. label = "rw-mrc-cache";
  47. reg = <0x003e0000 0x00010000>;
  48. };
  49. };
  50. };
  51. gpioa {
  52. compatible = "intel,ich6-gpio";
  53. u-boot,dm-pre-reloc;
  54. reg = <0 0x10>;
  55. bank-name = "A";
  56. };
  57. gpiob {
  58. compatible = "intel,ich6-gpio";
  59. u-boot,dm-pre-reloc;
  60. reg = <0x30 0x10>;
  61. bank-name = "B";
  62. };
  63. gpioc {
  64. compatible = "intel,ich6-gpio";
  65. u-boot,dm-pre-reloc;
  66. reg = <0x40 0x10>;
  67. bank-name = "C";
  68. };
  69. };
  70. };
  71. tpm {
  72. reg = <0xfed40000 0x5000>;
  73. compatible = "infineon,slb9635lpc";
  74. };
  75. };