chromebook_samus.dts 16 KB

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  1. /dts-v1/;
  2. #include <dt-bindings/gpio/x86-gpio.h>
  3. /include/ "skeleton.dtsi"
  4. /include/ "keyboard.dtsi"
  5. /include/ "serial.dtsi"
  6. /include/ "reset.dtsi"
  7. /include/ "rtc.dtsi"
  8. /include/ "tsc_timer.dtsi"
  9. /include/ "coreboot_fb.dtsi"
  10. / {
  11. model = "Google Samus";
  12. compatible = "google,samus", "intel,broadwell";
  13. aliases {
  14. spi0 = &spi;
  15. usb0 = &usb_0;
  16. usb1 = &usb_1;
  17. };
  18. config {
  19. silent_console = <0>;
  20. };
  21. cpus {
  22. #address-cells = <1>;
  23. #size-cells = <0>;
  24. cpu@0 {
  25. device_type = "cpu";
  26. compatible = "intel,core-i3-gen5";
  27. reg = <0>;
  28. intel,apic-id = <0>;
  29. intel,slow-ramp = <3>;
  30. };
  31. cpu@1 {
  32. device_type = "cpu";
  33. compatible = "intel,core-i3-gen5";
  34. reg = <1>;
  35. intel,apic-id = <1>;
  36. };
  37. cpu@2 {
  38. device_type = "cpu";
  39. compatible = "intel,core-i3-gen5";
  40. reg = <2>;
  41. intel,apic-id = <2>;
  42. };
  43. cpu@3 {
  44. device_type = "cpu";
  45. compatible = "intel,core-i3-gen5";
  46. reg = <3>;
  47. intel,apic-id = <3>;
  48. };
  49. };
  50. chosen {
  51. stdout-path = "/serial";
  52. };
  53. keyboard {
  54. intel,duplicate-por;
  55. };
  56. pch_pinctrl {
  57. compatible = "intel,x86-broadwell-pinctrl";
  58. u-boot,dm-pre-reloc;
  59. reg = <0 0>;
  60. /* Put this first: it is the default */
  61. gpio_unused: gpio-unused {
  62. mode-gpio;
  63. direction = <PIN_INPUT>;
  64. owner = <OWNER_GPIO>;
  65. sense-disable;
  66. };
  67. gpio_acpi_sci: acpi-sci {
  68. mode-gpio;
  69. direction = <PIN_INPUT>;
  70. invert;
  71. route = <ROUTE_SCI>;
  72. };
  73. gpio_acpi_smi: acpi-smi {
  74. mode-gpio;
  75. direction = <PIN_INPUT>;
  76. invert;
  77. route = <ROUTE_SMI>;
  78. };
  79. gpio_input: gpio-input {
  80. mode-gpio;
  81. direction = <PIN_INPUT>;
  82. owner = <OWNER_GPIO>;
  83. };
  84. gpio_input_invert: gpio-input-invert {
  85. mode-gpio;
  86. direction = <PIN_INPUT>;
  87. owner = <OWNER_GPIO>;
  88. invert;
  89. };
  90. gpio_native: gpio-native {
  91. };
  92. gpio_out_high: gpio-out-high {
  93. mode-gpio;
  94. direction = <PIN_OUTPUT>;
  95. output-value = <1>;
  96. owner = <OWNER_GPIO>;
  97. sense-disable;
  98. };
  99. gpio_out_low: gpio-out-low {
  100. mode-gpio;
  101. direction = <PIN_OUTPUT>;
  102. output-value = <0>;
  103. owner = <OWNER_GPIO>;
  104. sense-disable;
  105. };
  106. gpio_pirq: gpio-pirq {
  107. mode-gpio;
  108. direction = <PIN_INPUT>;
  109. owner = <OWNER_GPIO>;
  110. pirq-apic = <PIRQ_APIC_ROUTE>;
  111. };
  112. soc_gpio@0 {
  113. config =
  114. <0 &gpio_unused 0>, /* unused */
  115. <1 &gpio_unused 0>, /* unused */
  116. <2 &gpio_unused 0>, /* unused */
  117. <3 &gpio_unused 0>, /* unused */
  118. <4 &gpio_native 0>, /* native: i2c0_sda_gpio4 */
  119. <5 &gpio_native 0>, /* native: i2c0_scl_gpio5 */
  120. <6 &gpio_native 0>, /* native: i2c1_sda_gpio6 */
  121. <7 &gpio_native 0>, /* native: i2c1_scl_gpio7 */
  122. <8 &gpio_acpi_sci 0>, /* pch_lte_wake_l */
  123. <9 &gpio_input_invert 0>, /* trackpad_int_l (wake) */
  124. <10 &gpio_acpi_sci 0>, /* pch_wlan_wake_l */
  125. <11 &gpio_unused 0>, /* unused */
  126. <12 &gpio_unused 0>, /* unused */
  127. <13 &gpio_pirq 3>, /* trackpad_int_l (pirql) */
  128. <14 &gpio_pirq 4>, /* touch_int_l (pirqm) */
  129. <15 &gpio_unused 0>, /* unused (strap) */
  130. <16 &gpio_input 0>, /* pch_wp */
  131. <17 &gpio_unused 0>, /* unused */
  132. <18 &gpio_unused 0>, /* unused */
  133. <19 &gpio_unused 0>, /* unused */
  134. <20 &gpio_native 0>, /* pcie_wlan_clkreq_l */
  135. <21 &gpio_out_high 0>, /* pp3300_ssd_en */
  136. <22 &gpio_unused 0>, /* unused */
  137. <23 &gpio_out_low 0>, /* pp3300_autobahn_en */
  138. <24 &gpio_unused 0>, /* unused */
  139. <25 &gpio_input 0>, /* ec_in_rw */
  140. <26 &gpio_unused 0>, /* unused */
  141. <27 &gpio_acpi_sci 0>, /* pch_wake_l */
  142. <28 &gpio_unused 0>, /* unused */
  143. <29 &gpio_unused 0>, /* unused */
  144. <30 &gpio_native 0>, /* native: pch_suswarn_l */
  145. <31 &gpio_native 0>, /* native: acok_buf */
  146. <32 &gpio_native 0>, /* native: lpc_clkrun_l */
  147. <33 &gpio_native 0>, /* native: ssd_devslp */
  148. <34 &gpio_acpi_smi 0>, /* ec_smi_l */
  149. <35 &gpio_acpi_smi 0>, /* pch_nmi_dbg_l (route in nmi_en) */
  150. <36 &gpio_acpi_sci 0>, /* ec_sci_l */
  151. <37 &gpio_unused 0>, /* unused */
  152. <38 &gpio_unused 0>, /* unused */
  153. <39 &gpio_unused 0>, /* unused */
  154. <40 &gpio_native 0>, /* native: pch_usb1_oc_l */
  155. <41 &gpio_native 0>, /* native: pch_usb2_oc_l */
  156. <42 &gpio_unused 0>, /* wlan_disable_l */
  157. <43 &gpio_out_high 0>, /* pp1800_codec_en */
  158. <44 &gpio_unused 0>, /* unused */
  159. <45 &gpio_acpi_sci 0>, /* dsp_int - codec wake */
  160. <46 &gpio_pirq 6>, /* hotword_det_l_3v3 (pirqo) - codec irq */
  161. <47 &gpio_out_low 0>, /* ssd_reset_l */
  162. <48 &gpio_unused 0>, /* unused */
  163. <49 &gpio_unused 0>, /* unused */
  164. <50 &gpio_unused 0>, /* unused */
  165. <51 &gpio_unused 0>, /* unused */
  166. <52 &gpio_input 0>, /* sim_det */
  167. <53 &gpio_unused 0>, /* unused */
  168. <54 &gpio_unused 0>, /* unused */
  169. <55 &gpio_unused 0>, /* unused */
  170. <56 &gpio_unused 0>, /* unused */
  171. <57 &gpio_out_high 0>, /* codec_reset_l */
  172. <58 &gpio_unused 0>, /* unused */
  173. <59 &gpio_out_high 0>, /* lte_disable_l */
  174. <60 &gpio_unused 0>, /* unused */
  175. <61 &gpio_native 0>, /* native: pch_sus_stat */
  176. <62 &gpio_native 0>, /* native: pch_susclk */
  177. <63 &gpio_native 0>, /* native: pch_slp_s5_l */
  178. <64 &gpio_unused 0>, /* unused */
  179. <65 &gpio_input 0>, /* ram_id3 */
  180. <66 &gpio_input 0>, /* ram_id3_old (strap) */
  181. <67 &gpio_input 0>, /* ram_id0 */
  182. <68 &gpio_input 0>, /* ram_id1 */
  183. <69 &gpio_input 0>, /* ram_id2 */
  184. <70 &gpio_unused 0>, /* unused */
  185. <71 &gpio_native 0>, /* native: modphy_en */
  186. <72 &gpio_unused 0>, /* unused */
  187. <73 &gpio_unused 0>, /* unused */
  188. <74 &gpio_unused 0>, /* unused */
  189. <75 &gpio_unused 0>, /* unused */
  190. <76 &gpio_unused 0>, /* unused */
  191. <77 &gpio_unused 0>, /* unused */
  192. <78 &gpio_unused 0>, /* unused */
  193. <79 &gpio_unused 0>, /* unused */
  194. <80 &gpio_unused 0>, /* unused */
  195. <81 &gpio_unused 0>, /* unused */
  196. <82 &gpio_native 0>, /* native: ec_rcin_l */
  197. <83 &gpio_native 0>, /* gspi0_cs */
  198. <84 &gpio_native 0>, /* gspi0_clk */
  199. <85 &gpio_native 0>, /* gspi0_miso */
  200. <86 &gpio_native 0>, /* gspi0_mosi (strap) */
  201. <87 &gpio_unused 0>, /* unused */
  202. <88 &gpio_unused 0>, /* unused */
  203. <89 &gpio_out_high 0>, /* pp3300_sd_en */
  204. <90 &gpio_unused 0>, /* unused */
  205. <91 &gpio_unused 0>, /* unused */
  206. <92 &gpio_unused 0>, /* unused */
  207. <93 &gpio_unused 0>, /* unused */
  208. <94 &gpio_unused 0>; /* unused */
  209. };
  210. };
  211. pci {
  212. compatible = "pci-x86";
  213. #address-cells = <3>;
  214. #size-cells = <2>;
  215. u-boot,dm-pre-reloc;
  216. ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
  217. 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
  218. 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
  219. northbridge@0,0 {
  220. reg = <0x00000000 0 0 0 0>;
  221. compatible = "intel,broadwell-northbridge";
  222. board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
  223. <&gpio_c 3 0>, <&gpio_c 1 0>;
  224. u-boot,dm-pre-reloc;
  225. spd {
  226. #address-cells = <1>;
  227. #size-cells = <0>;
  228. samsung_4 {
  229. reg = <6>;
  230. data = [91 20 f1 03 04 11 05 0b
  231. 03 11 01 08 0a 00 50 01
  232. 78 78 90 50 90 11 50 e0
  233. 10 04 3c 3c 01 90 00 00
  234. 00 80 00 00 00 00 00 a8
  235. 00 00 00 00 00 00 00 00
  236. 00 00 00 00 00 00 00 00
  237. 00 00 00 00 0f 11 02 00
  238. 00 00 00 00 00 00 00 00
  239. 00 00 00 00 00 00 00 00
  240. 00 00 00 00 00 00 00 00
  241. 00 00 00 00 00 00 00 00
  242. 00 00 00 00 00 00 00 00
  243. 00 00 00 00 00 00 00 00
  244. 00 00 00 00 00 80 ce 01
  245. 00 00 55 00 00 00 00 00
  246. 4b 34 45 38 45 33 30 34
  247. 45 44 2d 45 47 43 45 20
  248. 20 20 00 00 80 ce 00 00
  249. 00 00 00 00 00 00 00 00
  250. 00 00 00 00 00 00 00 00
  251. 00 00 00 00 00 00 00 00
  252. 00 00 00 00 00 00 00 00
  253. 00 00 00 00 00 00 00 00
  254. 00 00 00 00 00 00 00 00
  255. 00 00 00 00 00 00 00 00
  256. 00 00 00 00 00 00 00 00
  257. 00 00 00 00 00 00 00 00
  258. 00 00 00 00 00 00 00 00
  259. 00 00 00 00 00 00 00 00
  260. 00 00 00 00 00 00 00 00
  261. 00 00 00 00 00 00 00 00];
  262. };
  263. hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
  264. /*
  265. * banks 8, ranks 2, rows 14,
  266. * columns 10, density 4096 mb, x32
  267. */
  268. reg = <8>;
  269. data = [91 20 f1 03 04 11 05 0b
  270. 03 11 01 08 0a 00 50 01
  271. 78 78 90 50 90 11 50 e0
  272. 10 04 3c 3c 01 90 00 00
  273. 00 80 00 00 00 00 00 a8
  274. 00 00 00 00 00 00 00 00
  275. 00 00 00 00 00 00 00 00
  276. 00 00 00 00 0f 01 02 00
  277. 00 00 00 00 00 00 00 00
  278. 00 00 00 00 00 00 00 00
  279. 00 00 00 00 00 00 00 00
  280. 00 00 00 00 00 00 00 00
  281. 00 00 00 00 00 00 00 00
  282. 00 00 00 00 00 00 00 00
  283. 00 00 00 00 00 80 ad 00
  284. 00 00 55 00 00 00 00 00
  285. 48 39 43 43 4e 4e 4e 42
  286. 4c 54 4d 4c 41 52 2d 4e
  287. 54 4d 00 00 80 ad 00 00
  288. 00 00 00 00 00 00 00 00
  289. 00 00 00 00 00 00 00 00
  290. 00 00 00 00 00 00 00 00
  291. 00 00 00 00 00 00 00 00
  292. 00 00 00 00 00 00 00 00
  293. 00 00 00 00 00 00 00 00
  294. 00 00 00 00 00 00 00 00
  295. 00 00 00 00 00 00 00 00
  296. 00 00 00 00 00 00 00 00
  297. 00 00 00 00 00 00 00 00
  298. 00 00 00 00 00 00 00 00
  299. 00 00 00 00 00 00 00 00
  300. 00 00 00 00 00 00 00 00];
  301. };
  302. samsung_8 {
  303. reg = <10>;
  304. data = [91 20 f1 03 04 12 05 0a
  305. 03 11 01 08 0a 00 50 01
  306. 78 78 90 50 90 11 50 e0
  307. 10 04 3c 3c 01 90 00 00
  308. 00 80 00 00 00 00 00 a8
  309. 00 00 00 00 00 00 00 00
  310. 00 00 00 00 00 00 00 00
  311. 00 00 00 00 0f 11 02 00
  312. 00 00 00 00 00 00 00 00
  313. 00 00 00 00 00 00 00 00
  314. 00 00 00 00 00 00 00 00
  315. 00 00 00 00 00 00 00 00
  316. 00 00 00 00 00 00 00 00
  317. 00 00 00 00 00 00 00 00
  318. 00 00 00 00 00 80 ce 01
  319. 00 00 55 00 00 00 00 00
  320. 4b 34 45 36 45 33 30 34
  321. 45 44 2d 45 47 43 45 20
  322. 20 20 00 00 80 ce 00 00
  323. 00 00 00 00 00 00 00 00
  324. 00 00 00 00 00 00 00 00
  325. 00 00 00 00 00 00 00 00
  326. 00 00 00 00 00 00 00 00
  327. 00 00 00 00 00 00 00 00
  328. 00 00 00 00 00 00 00 00
  329. 00 00 00 00 00 00 00 00
  330. 00 00 00 00 00 00 00 00
  331. 00 00 00 00 00 00 00 00
  332. 00 00 00 00 00 00 00 00
  333. 00 00 00 00 00 00 00 00
  334. 00 00 00 00 00 00 00 00
  335. 00 00 00 00 00 00 00 00];
  336. };
  337. hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
  338. /*
  339. * banks 8, ranks 2, rows 14,
  340. * columns 11, density 4096 mb, x16
  341. */
  342. reg = <12>;
  343. data = [91 20 f1 03 04 12 05 0a
  344. 03 11 01 08 0a 00 50 01
  345. 78 78 90 50 90 11 50 e0
  346. 10 04 3c 3c 01 90 00 00
  347. 00 80 00 00 00 00 00 a8
  348. 00 00 00 00 00 00 00 00
  349. 00 00 00 00 00 00 00 00
  350. 00 00 00 00 0f 01 02 00
  351. 00 00 00 00 00 00 00 00
  352. 00 00 00 00 00 00 00 00
  353. 00 00 00 00 00 00 00 00
  354. 00 00 00 00 00 00 00 00
  355. 00 00 00 00 00 00 00 00
  356. 00 00 00 00 00 00 00 00
  357. 00 00 00 00 00 80 ad 00
  358. 00 00 55 00 00 00 00 00
  359. 48 39 43 43 4e 4e 4e 42
  360. 4c 54 4d 4c 41 52 2d 4e
  361. 54 4d 00 00 80 ad 00 00
  362. 00 00 00 00 00 00 00 00
  363. 00 00 00 00 00 00 00 00
  364. 00 00 00 00 00 00 00 00
  365. 00 00 00 00 00 00 00 00
  366. 00 00 00 00 00 00 00 00
  367. 00 00 00 00 00 00 00 00
  368. 00 00 00 00 00 00 00 00
  369. 00 00 00 00 00 00 00 00
  370. 00 00 00 00 00 00 00 00
  371. 00 00 00 00 00 00 00 00
  372. 00 00 00 00 00 00 00 00
  373. 00 00 00 00 00 00 00 00
  374. 00 00 00 00 00 00 00 00];
  375. };
  376. hynix-h9ccnnncltmlar-lpddr3 {
  377. /*
  378. * banks 8, ranks 2, rows 15,
  379. * columns 11, density 8192 mb, x16
  380. */
  381. reg = <13>;
  382. data = [91 20 f1 03 05 1a 05 0a
  383. 03 11 01 08 0a 00 50 01
  384. 78 78 90 50 90 11 50 e0
  385. 90 06 3c 3c 01 90 00 00
  386. 00 80 00 00 00 00 00 a8
  387. 00 00 00 00 00 00 00 00
  388. 00 00 00 00 00 00 00 00
  389. 00 00 00 00 0f 01 02 00
  390. 00 00 00 00 00 00 00 00
  391. 00 00 00 00 00 00 00 00
  392. 00 00 00 00 00 00 00 00
  393. 00 00 00 00 00 00 00 00
  394. 00 00 00 00 00 00 00 00
  395. 00 00 00 00 00 00 00 00
  396. 00 00 00 00 00 80 ad 00
  397. 00 00 55 00 00 00 00 00
  398. 48 39 43 43 4e 4e 4e 43
  399. 4c 54 4d 4c 41 52 00 00
  400. 00 00 00 00 80 ad 00 00
  401. 00 00 00 00 00 00 00 00
  402. 00 00 00 00 00 00 00 00
  403. 00 00 00 00 00 00 00 00
  404. 00 00 00 00 00 00 00 00
  405. 00 00 00 00 00 00 00 00
  406. 00 00 00 00 00 00 00 00
  407. 00 00 00 00 00 00 00 00
  408. 00 00 00 00 00 00 00 00
  409. 00 00 00 00 00 00 00 00
  410. 00 00 00 00 00 00 00 00
  411. 00 00 00 00 00 00 00 00
  412. 00 00 00 00 00 00 00 00
  413. 00 00 00 00 00 00 00 00];
  414. };
  415. elpida-edfb232a1ma {
  416. /*
  417. * banks 8, ranks 2, rows 15,
  418. * columns 11, density 8192 mb, x16
  419. */
  420. reg = <15>;
  421. data = [91 20 f1 03 05 1a 05 0a
  422. 03 11 01 08 0a 00 50 01
  423. 78 78 90 50 90 11 50 e0
  424. 90 06 3c 3c 01 90 00 00
  425. 00 80 00 00 00 00 00 a8
  426. 00 00 00 00 00 00 00 00
  427. 00 00 00 00 00 00 00 00
  428. 00 00 00 00 0f 01 02 00
  429. 00 00 00 00 00 00 00 00
  430. 00 00 00 00 00 00 00 00
  431. 00 00 00 00 00 00 00 00
  432. 00 00 00 00 00 00 00 00
  433. 00 00 00 00 00 00 00 00
  434. 00 00 00 00 00 00 00 00
  435. 00 00 00 00 00 02 fe 00
  436. 00 00 00 00 00 00 00 00
  437. 45 44 46 42 32 33 32 41
  438. 31 4d 41 2d 47 44 2d 46
  439. 00 00 00 00 02 fe 00 00
  440. 00 00 00 00 00 00 00 00
  441. 00 00 00 00 00 00 00 00
  442. 00 00 00 00 00 00 00 00
  443. 00 00 00 00 00 00 00 00
  444. 00 00 00 00 00 00 00 00
  445. 00 00 00 00 00 00 00 00
  446. 00 00 00 00 00 00 00 00
  447. 00 00 00 00 00 00 00 00
  448. 00 00 00 00 00 00 00 00
  449. 00 00 00 00 00 00 00 00
  450. 00 00 00 00 00 00 00 00
  451. 00 00 00 00 00 00 00 00
  452. 00 00 00 00 00 00 00 00];
  453. };
  454. };
  455. };
  456. gma@2,0 {
  457. reg = <0x00001000 0 0 0 0>;
  458. compatible = "intel,broadwell-igd";
  459. intel,dp-hotplug = <6 6 6>;
  460. intel,port-select = <1>; /* eDP */
  461. intel,power-cycle-delay = <6>;
  462. intel,power-up-delay = <2000>;
  463. intel,power-down-delay = <500>;
  464. intel,power-backlight-on-delay = <2000>;
  465. intel,power-backlight-off-delay = <2000>;
  466. intel,cpu-backlight = <0x00000200>;
  467. intel,pch-backlight = <0x04000200>;
  468. intel,pre-graphics-delay = <200>;
  469. };
  470. me@16,0 {
  471. reg = <0x0000b000 0 0 0 0>;
  472. compatible = "intel,me";
  473. u-boot,dm-pre-reloc;
  474. };
  475. usb_1: usb@14,0 {
  476. reg = <0x0000a000 0 0 0 0>;
  477. compatible = "xhci-pci";
  478. };
  479. usb_0: usb@1d,0 {
  480. status = "disabled";
  481. reg = <0x0000e800 0 0 0 0>;
  482. compatible = "ehci-pci";
  483. };
  484. pch@1f,0 {
  485. reg = <0x0000f800 0 0 0 0>;
  486. compatible = "intel,broadwell-pch";
  487. u-boot,dm-pre-reloc;
  488. #address-cells = <1>;
  489. #size-cells = <1>;
  490. intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
  491. 0x80 0x80 0x80 0x80>;
  492. intel,gpi-routing = <0 0 0 0 0 0 0 2
  493. 1 0 0 0 0 0 0 0>;
  494. /* Enable EC SMI source */
  495. intel,alt-gp-smi-enable = <0x0040>;
  496. /* EC-SCI is GPIO36 */
  497. intel,gpe0-en = <0 0x10 0 0>;
  498. power-enable-gpio = <&gpio_a 23 0>;
  499. spi: spi {
  500. #address-cells = <1>;
  501. #size-cells = <0>;
  502. compatible = "intel,ich9-spi";
  503. spi-flash@0 {
  504. #size-cells = <1>;
  505. #address-cells = <1>;
  506. reg = <0>;
  507. compatible = "winbond,w25q64",
  508. "spi-flash";
  509. memory-map = <0xff800000 0x00800000>;
  510. rw-mrc-cache {
  511. label = "rw-mrc-cache";
  512. reg = <0x003e0000 0x00010000>;
  513. };
  514. };
  515. };
  516. gpio_a: gpioa {
  517. compatible = "intel,broadwell-gpio";
  518. u-boot,dm-pre-reloc;
  519. #gpio-cells = <2>;
  520. gpio-controller;
  521. reg = <0 0>;
  522. bank-name = "A";
  523. };
  524. gpio_b: gpiob {
  525. compatible = "intel,broadwell-gpio";
  526. u-boot,dm-pre-reloc;
  527. #gpio-cells = <2>;
  528. gpio-controller;
  529. reg = <1 0>;
  530. bank-name = "B";
  531. };
  532. gpio_c: gpioc {
  533. compatible = "intel,broadwell-gpio";
  534. u-boot,dm-pre-reloc;
  535. #gpio-cells = <2>;
  536. gpio-controller;
  537. reg = <2 0>;
  538. bank-name = "C";
  539. };
  540. lpc {
  541. compatible = "intel,broadwell-lpc";
  542. #address-cells = <1>;
  543. #size-cells = <0>;
  544. u-boot,dm-pre-reloc;
  545. intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
  546. cros-ec@200 {
  547. compatible = "google,cros-ec-lpc";
  548. reg = <0x204 1 0x200 1 0x880 0x80>;
  549. /*
  550. * Describes the flash memory within
  551. * the EC
  552. */
  553. #address-cells = <1>;
  554. #size-cells = <1>;
  555. flash@8000000 {
  556. reg = <0x08000000 0x20000>;
  557. erase-value = <0xff>;
  558. };
  559. };
  560. };
  561. };
  562. sata@1f,2 {
  563. compatible = "intel,wildcatpoint-ahci";
  564. reg = <0x0000fa00 0 0 0 0>;
  565. u-boot,dm-pre-reloc;
  566. intel,sata-mode = "ahci";
  567. intel,sata-port-map = <1>;
  568. intel,sata-port0-gen3-tx = <0x72>;
  569. reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>;
  570. };
  571. smbus: smbus@1f,3 {
  572. compatible = "intel,ich-i2c";
  573. reg = <0x0000fb00 0 0 0 0>;
  574. u-boot,dm-pre-reloc;
  575. };
  576. };
  577. tpm {
  578. reg = <0xfed40000 0x5000>;
  579. compatible = "infineon,slb9635lpc";
  580. };
  581. microcode {
  582. update@0 {
  583. #include "microcode/mc0306d4_00000018.dtsi"
  584. };
  585. };
  586. };