encoding.h 5.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2017 Microsemi Corporation.
  4. * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com>
  5. */
  6. #ifndef RISCV_CSR_ENCODING_H
  7. #define RISCV_CSR_ENCODING_H
  8. #define MSTATUS_UIE 0x00000001
  9. #define MSTATUS_SIE 0x00000002
  10. #define MSTATUS_HIE 0x00000004
  11. #define MSTATUS_MIE 0x00000008
  12. #define MSTATUS_UPIE 0x00000010
  13. #define MSTATUS_SPIE 0x00000020
  14. #define MSTATUS_HPIE 0x00000040
  15. #define MSTATUS_MPIE 0x00000080
  16. #define MSTATUS_SPP 0x00000100
  17. #define MSTATUS_HPP 0x00000600
  18. #define MSTATUS_MPP 0x00001800
  19. #define MSTATUS_FS 0x00006000
  20. #define MSTATUS_XS 0x00018000
  21. #define MSTATUS_MPRV 0x00020000
  22. #define MSTATUS_PUM 0x00040000
  23. #define MSTATUS_VM 0x1F000000
  24. #define MSTATUS32_SD 0x80000000
  25. #define MSTATUS64_SD 0x8000000000000000
  26. #define MCAUSE32_CAUSE 0x7FFFFFFF
  27. #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF
  28. #define MCAUSE32_INT 0x80000000
  29. #define MCAUSE64_INT 0x8000000000000000
  30. #define SSTATUS_UIE 0x00000001
  31. #define SSTATUS_SIE 0x00000002
  32. #define SSTATUS_UPIE 0x00000010
  33. #define SSTATUS_SPIE 0x00000020
  34. #define SSTATUS_SPP 0x00000100
  35. #define SSTATUS_FS 0x00006000
  36. #define SSTATUS_XS 0x00018000
  37. #define SSTATUS_PUM 0x00040000
  38. #define SSTATUS32_SD 0x80000000
  39. #define SSTATUS64_SD 0x8000000000000000
  40. #define MIP_SSIP BIT(IRQ_S_SOFT)
  41. #define MIP_HSIP BIT(IRQ_H_SOFT)
  42. #define MIP_MSIP BIT(IRQ_M_SOFT)
  43. #define MIP_STIP BIT(IRQ_S_TIMER)
  44. #define MIP_HTIP BIT(IRQ_H_TIMER)
  45. #define MIP_MTIP BIT(IRQ_M_TIMER)
  46. #define MIP_SEIP BIT(IRQ_S_EXT)
  47. #define MIP_HEIP BIT(IRQ_H_EXT)
  48. #define MIP_MEIP BIT(IRQ_M_EXT)
  49. #define SIP_SSIP MIP_SSIP
  50. #define SIP_STIP MIP_STIP
  51. #define PRV_U 0
  52. #define PRV_S 1
  53. #define PRV_H 2
  54. #define PRV_M 3
  55. #define VM_MBARE 0
  56. #define VM_MBB 1
  57. #define VM_MBBID 2
  58. #define VM_SV32 8
  59. #define VM_SV39 9
  60. #define VM_SV48 10
  61. #define IRQ_S_SOFT 1
  62. #define IRQ_H_SOFT 2
  63. #define IRQ_M_SOFT 3
  64. #define IRQ_S_TIMER 5
  65. #define IRQ_H_TIMER 6
  66. #define IRQ_M_TIMER 7
  67. #define IRQ_S_EXT 9
  68. #define IRQ_H_EXT 10
  69. #define IRQ_M_EXT 11
  70. #define IRQ_COP 12
  71. #define IRQ_HOST 13
  72. #define DEFAULT_RSTVEC 0x00001000
  73. #define DEFAULT_NMIVEC 0x00001004
  74. #define DEFAULT_MTVEC 0x00001010
  75. #define CONFIG_STRING_ADDR 0x0000100C
  76. #define EXT_IO_BASE 0x40000000
  77. #define DRAM_BASE 0x80000000
  78. // page table entry (PTE) fields
  79. #define PTE_V 0x001 // Valid
  80. #define PTE_TYPE 0x01E // Type
  81. #define PTE_R 0x020 // Referenced
  82. #define PTE_D 0x040 // Dirty
  83. #define PTE_SOFT 0x380 // Reserved for Software
  84. #define PTE_TYPE_TABLE 0x00
  85. #define PTE_TYPE_TABLE_GLOBAL 0x02
  86. #define PTE_TYPE_URX_SR 0x04
  87. #define PTE_TYPE_URWX_SRW 0x06
  88. #define PTE_TYPE_UR_SR 0x08
  89. #define PTE_TYPE_URW_SRW 0x0A
  90. #define PTE_TYPE_URX_SRX 0x0C
  91. #define PTE_TYPE_URWX_SRWX0x0E
  92. #define PTE_TYPE_SR 0x10
  93. #define PTE_TYPE_SRW 0x12
  94. #define PTE_TYPE_SRX 0x14
  95. #define PTE_TYPE_SRWX 0x16
  96. #define PTE_TYPE_SR_GLOBAL 0x18
  97. #define PTE_TYPE_SRW_GLOBAL 0x1A
  98. #define PTE_TYPE_SRX_GLOBAL 0x1C
  99. #define PTE_TYPE_SRWX_GLOBAL 0x1E
  100. #define PTE_PPN_SHIFT 10
  101. #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1)
  102. #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1)
  103. #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1)
  104. #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1)
  105. #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1)
  106. #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1)
  107. #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1)
  108. #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \
  109. typeof(_PTE) (PTE) = (_PTE); \
  110. typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \
  111. ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \
  112. (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \
  113. ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE)))
  114. #ifdef __riscv
  115. #ifdef CONFIG_64BIT
  116. # define MSTATUS_SD MSTATUS64_SD
  117. # define SSTATUS_SD SSTATUS64_SD
  118. # define MCAUSE_INT MCAUSE64_INT
  119. # define MCAUSE_CAUSE MCAUSE64_CAUSE
  120. # define RISCV_PGLEVEL_BITS 9
  121. #else
  122. # define MSTATUS_SD MSTATUS32_SD
  123. # define SSTATUS_SD SSTATUS32_SD
  124. # define RISCV_PGLEVEL_BITS 10
  125. # define MCAUSE_INT MCAUSE32_INT
  126. # define MCAUSE_CAUSE MCAUSE32_CAUSE
  127. #endif
  128. #define RISCV_PGSHIFT 12
  129. #define RISCV_PGSIZE BIT(RISCV_PGSHIFT)
  130. #ifndef __ASSEMBLER__
  131. #ifdef __GNUC__
  132. #define read_csr(reg) ({ unsigned long __tmp; \
  133. asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
  134. __tmp; })
  135. #define write_csr(reg, _val) ({ \
  136. typeof(_val) (val) = (_val); \
  137. if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
  138. asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
  139. else \
  140. asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
  141. #define swap_csr(reg, _val) ({ unsigned long __tmp; \
  142. typeof(_val) (val) = (_val); \
  143. if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
  144. asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
  145. else \
  146. asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
  147. __tmp; })
  148. #define set_csr(reg, _bit) ({ unsigned long __tmp; \
  149. typeof(_bit) (bit) = (_bit); \
  150. if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
  151. asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
  152. else \
  153. asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
  154. __tmp; })
  155. #define clear_csr(reg, _bit) ({ unsigned long __tmp; \
  156. typeof(_bit) (bit) = (_bit); \
  157. if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
  158. asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
  159. else \
  160. asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
  161. __tmp; })
  162. #define rdtime() read_csr(time)
  163. #define rdcycle() read_csr(cycle)
  164. #define rdinstret() read_csr(instret)
  165. #endif
  166. #endif
  167. #endif
  168. #endif