cache.h 577 B

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2017 Andes Technology Corporation
  4. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  5. */
  6. #ifndef _ASM_RISCV_CACHE_H
  7. #define _ASM_RISCV_CACHE_H
  8. /*
  9. * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
  10. * We use that value for aligning DMA buffers unless the board config has
  11. * specified an alternate cache line size.
  12. */
  13. #ifdef CONFIG_SYS_CACHELINE_SIZE
  14. #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
  15. #else
  16. #define ARCH_DMA_MINALIGN 32
  17. #endif
  18. #endif /* _ASM_RISCV_CACHE_H */