brcm,bcm6362.dtsi 4.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
  4. */
  5. #include <dt-bindings/clock/bcm6362-clock.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/power-domain/bcm6362-power-domain.h>
  8. #include <dt-bindings/reset/bcm6362-reset.h>
  9. #include "skeleton.dtsi"
  10. / {
  11. compatible = "brcm,bcm6362";
  12. aliases {
  13. spi0 = &lsspi;
  14. spi1 = &hsspi;
  15. };
  16. cpus {
  17. reg = <0x10000000 0x4>;
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. u-boot,dm-pre-reloc;
  21. cpu@0 {
  22. compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
  23. device_type = "cpu";
  24. reg = <0>;
  25. u-boot,dm-pre-reloc;
  26. };
  27. cpu@1 {
  28. compatible = "brcm,bcm6362-cpu", "mips,mips4Kc";
  29. device_type = "cpu";
  30. reg = <1>;
  31. u-boot,dm-pre-reloc;
  32. };
  33. };
  34. clocks {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. u-boot,dm-pre-reloc;
  39. hsspi_pll: hsspi-pll {
  40. compatible = "fixed-clock";
  41. #clock-cells = <0>;
  42. clock-frequency = <133333333>;
  43. };
  44. periph_osc: periph-osc {
  45. compatible = "fixed-clock";
  46. #clock-cells = <0>;
  47. clock-frequency = <50000000>;
  48. u-boot,dm-pre-reloc;
  49. };
  50. periph_clk: periph-clk {
  51. compatible = "brcm,bcm6345-clk";
  52. reg = <0x10000004 0x4>;
  53. #clock-cells = <1>;
  54. };
  55. };
  56. ubus {
  57. compatible = "simple-bus";
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. u-boot,dm-pre-reloc;
  61. pll_cntl: syscon@10000008 {
  62. compatible = "syscon";
  63. reg = <0x10000008 0x4>;
  64. };
  65. syscon-reboot {
  66. compatible = "syscon-reboot";
  67. regmap = <&pll_cntl>;
  68. offset = <0x0>;
  69. mask = <0x1>;
  70. };
  71. periph_rst: reset-controller@10000010 {
  72. compatible = "brcm,bcm6345-reset";
  73. reg = <0x10000010 0x4>;
  74. #reset-cells = <1>;
  75. };
  76. wdt: watchdog@1000005c {
  77. compatible = "brcm,bcm6345-wdt";
  78. reg = <0x1000005c 0xc>;
  79. clocks = <&periph_osc>;
  80. };
  81. wdt-reboot {
  82. compatible = "wdt-reboot";
  83. wdt = <&wdt>;
  84. };
  85. gpio1: gpio-controller@10000080 {
  86. compatible = "brcm,bcm6345-gpio";
  87. reg = <0x10000080 0x4>, <0x10000088 0x4>;
  88. gpio-controller;
  89. #gpio-cells = <2>;
  90. ngpios = <16>;
  91. status = "disabled";
  92. };
  93. gpio0: gpio-controller@10000084 {
  94. compatible = "brcm,bcm6345-gpio";
  95. reg = <0x10000084 0x4>, <0x1000008c 0x4>;
  96. gpio-controller;
  97. #gpio-cells = <2>;
  98. status = "disabled";
  99. };
  100. uart0: serial@10000100 {
  101. compatible = "brcm,bcm6345-uart";
  102. reg = <0x10000100 0x18>;
  103. clocks = <&periph_osc>;
  104. status = "disabled";
  105. };
  106. uart1: serial@10000120 {
  107. compatible = "brcm,bcm6345-uart";
  108. reg = <0x10000120 0x18>;
  109. clocks = <&periph_osc>;
  110. status = "disabled";
  111. };
  112. lsspi: spi@10000800 {
  113. compatible = "brcm,bcm6358-spi";
  114. reg = <0x10000800 0x70c>;
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. clocks = <&periph_clk BCM6362_CLK_SPI>;
  118. resets = <&periph_rst BCM6362_RST_SPI>;
  119. spi-max-frequency = <20000000>;
  120. num-cs = <8>;
  121. status = "disabled";
  122. };
  123. hsspi: spi@10001000 {
  124. compatible = "brcm,bcm6328-hsspi";
  125. #address-cells = <1>;
  126. #size-cells = <0>;
  127. reg = <0x10001000 0x600>;
  128. clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>;
  129. clock-names = "hsspi", "pll";
  130. resets = <&periph_rst BCM6362_RST_SPI>;
  131. spi-max-frequency = <50000000>;
  132. num-cs = <8>;
  133. status = "disabled";
  134. };
  135. leds: led-controller@10001900 {
  136. compatible = "brcm,bcm6328-leds";
  137. reg = <0x10001900 0x24>;
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. status = "disabled";
  141. };
  142. periph_pwr: power-controller@10001848 {
  143. compatible = "brcm,bcm6328-power-domain";
  144. reg = <0x10001848 0x4>;
  145. #power-domain-cells = <1>;
  146. };
  147. ehci: usb-controller@10002500 {
  148. compatible = "brcm,bcm6362-ehci", "generic-ehci";
  149. reg = <0x10002500 0x100>;
  150. phys = <&usbh>;
  151. big-endian;
  152. status = "disabled";
  153. };
  154. ohci: usb-controller@10002600 {
  155. compatible = "brcm,bcm6362-ohci", "generic-ohci";
  156. reg = <0x10002600 0x100>;
  157. phys = <&usbh>;
  158. big-endian;
  159. status = "disabled";
  160. };
  161. usbh: usb-phy@10002700 {
  162. compatible = "brcm,bcm6368-usbh";
  163. reg = <0x10002700 0x38>;
  164. #phy-cells = <0>;
  165. clocks = <&periph_clk BCM6362_CLK_USBH>;
  166. clock-names = "usbh";
  167. power-domains = <&periph_pwr BCM6362_PWR_USBH>;
  168. resets = <&periph_rst BCM6362_RST_USBH>;
  169. status = "disabled";
  170. };
  171. memory-controller@10003000 {
  172. compatible = "brcm,bcm6328-mc";
  173. reg = <0x10003000 0x864>;
  174. u-boot,dm-pre-reloc;
  175. };
  176. };
  177. };