brcm,bcm6328.dtsi 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. */
  5. #include <dt-bindings/clock/bcm6328-clock.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/power-domain/bcm6328-power-domain.h>
  8. #include <dt-bindings/reset/bcm6328-reset.h>
  9. #include "skeleton.dtsi"
  10. / {
  11. compatible = "brcm,bcm6328";
  12. aliases {
  13. spi0 = &spi;
  14. };
  15. cpus {
  16. reg = <0x10000000 0x4>;
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. u-boot,dm-pre-reloc;
  20. cpu@0 {
  21. compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
  22. device_type = "cpu";
  23. reg = <0>;
  24. u-boot,dm-pre-reloc;
  25. };
  26. cpu@1 {
  27. compatible = "brcm,bcm6328-cpu", "mips,mips4Kc";
  28. device_type = "cpu";
  29. reg = <1>;
  30. u-boot,dm-pre-reloc;
  31. };
  32. };
  33. clocks {
  34. compatible = "simple-bus";
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. u-boot,dm-pre-reloc;
  38. hsspi_pll: hsspi-pll {
  39. compatible = "fixed-clock";
  40. #clock-cells = <0>;
  41. clock-frequency = <133333333>;
  42. };
  43. periph_osc: periph-osc {
  44. compatible = "fixed-clock";
  45. #clock-cells = <0>;
  46. clock-frequency = <50000000>;
  47. u-boot,dm-pre-reloc;
  48. };
  49. periph_clk: periph-clk {
  50. compatible = "brcm,bcm6345-clk";
  51. reg = <0x10000004 0x4>;
  52. #clock-cells = <1>;
  53. };
  54. };
  55. ubus {
  56. compatible = "simple-bus";
  57. #address-cells = <1>;
  58. #size-cells = <1>;
  59. u-boot,dm-pre-reloc;
  60. periph_rst: reset-controller@10000010 {
  61. compatible = "brcm,bcm6345-reset";
  62. reg = <0x10000010 0x4>;
  63. #reset-cells = <1>;
  64. };
  65. pll_cntl: syscon@10000068 {
  66. compatible = "syscon";
  67. reg = <0x10000068 0x4>;
  68. };
  69. syscon-reboot {
  70. compatible = "syscon-reboot";
  71. regmap = <&pll_cntl>;
  72. offset = <0x0>;
  73. mask = <0x1>;
  74. };
  75. wdt: watchdog@1000005c {
  76. compatible = "brcm,bcm6345-wdt";
  77. reg = <0x1000005c 0xc>;
  78. clocks = <&periph_osc>;
  79. };
  80. wdt-reboot {
  81. compatible = "wdt-reboot";
  82. wdt = <&wdt>;
  83. };
  84. gpio: gpio-controller@10000084 {
  85. compatible = "brcm,bcm6345-gpio";
  86. reg = <0x10000084 0x4>, <0x1000008c 0x4>;
  87. gpio-controller;
  88. #gpio-cells = <2>;
  89. status = "disabled";
  90. };
  91. uart0: serial@10000100 {
  92. compatible = "brcm,bcm6345-uart";
  93. reg = <0x10000100 0x18>;
  94. clocks = <&periph_osc>;
  95. status = "disabled";
  96. };
  97. uart1: serial@10000120 {
  98. compatible = "brcm,bcm6345-uart";
  99. reg = <0x10000120 0x18>;
  100. clocks = <&periph_osc>;
  101. status = "disabled";
  102. };
  103. leds: led-controller@10000800 {
  104. compatible = "brcm,bcm6328-leds";
  105. reg = <0x10000800 0x24>;
  106. #address-cells = <1>;
  107. #size-cells = <0>;
  108. status = "disabled";
  109. };
  110. spi: spi@10001000 {
  111. compatible = "brcm,bcm6328-hsspi";
  112. #address-cells = <1>;
  113. #size-cells = <0>;
  114. reg = <0x10001000 0x600>;
  115. clocks = <&periph_clk BCM6328_CLK_HSSPI>, <&hsspi_pll>;
  116. clock-names = "hsspi", "pll";
  117. resets = <&periph_rst BCM6328_RST_SPI>;
  118. spi-max-frequency = <33333334>;
  119. num-cs = <3>;
  120. status = "disabled";
  121. };
  122. periph_pwr: power-controller@10001848 {
  123. compatible = "brcm,bcm6328-power-domain";
  124. reg = <0x10001848 0x4>;
  125. #power-domain-cells = <1>;
  126. };
  127. ehci: usb-controller@10002500 {
  128. compatible = "brcm,bcm6328-ehci", "generic-ehci";
  129. reg = <0x10002500 0x100>;
  130. phys = <&usbh>;
  131. big-endian;
  132. status = "disabled";
  133. };
  134. ohci: usb-controller@10002600 {
  135. compatible = "brcm,bcm6328-ohci", "generic-ohci";
  136. reg = <0x10002600 0x100>;
  137. phys = <&usbh>;
  138. big-endian;
  139. status = "disabled";
  140. };
  141. usbh: usb-phy@10002700 {
  142. compatible = "brcm,bcm6328-usbh";
  143. reg = <0x10002700 0x38>;
  144. #phy-cells = <0>;
  145. clocks = <&periph_clk BCM6328_CLK_USBH>;
  146. clock-names = "usbh";
  147. power-domains = <&periph_pwr BCM6328_PWR_USBH>;
  148. resets = <&periph_rst BCM6328_RST_USBH>;
  149. status = "disabled";
  150. };
  151. memory-controller@10003000 {
  152. compatible = "brcm,bcm6328-mc";
  153. reg = <0x10003000 0x864>;
  154. u-boot,dm-pre-reloc;
  155. };
  156. };
  157. };