brcm,bcm63268.dtsi 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. */
  5. #include <dt-bindings/clock/bcm63268-clock.h>
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/power-domain/bcm63268-power-domain.h>
  8. #include <dt-bindings/reset/bcm63268-reset.h>
  9. #include "skeleton.dtsi"
  10. / {
  11. compatible = "brcm,bcm63268";
  12. aliases {
  13. spi0 = &lsspi;
  14. spi1 = &hsspi;
  15. };
  16. cpus {
  17. reg = <0x10000000 0x4>;
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. u-boot,dm-pre-reloc;
  21. cpu@0 {
  22. compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
  23. device_type = "cpu";
  24. reg = <0>;
  25. u-boot,dm-pre-reloc;
  26. };
  27. cpu@1 {
  28. compatible = "brcm,bcm63268-cpu", "mips,mips4Kc";
  29. device_type = "cpu";
  30. reg = <1>;
  31. u-boot,dm-pre-reloc;
  32. };
  33. };
  34. clocks {
  35. compatible = "simple-bus";
  36. #address-cells = <1>;
  37. #size-cells = <1>;
  38. u-boot,dm-pre-reloc;
  39. hsspi_pll: hsspi-pll {
  40. compatible = "fixed-clock";
  41. #clock-cells = <0>;
  42. clock-frequency = <400000000>;
  43. };
  44. periph_osc: periph-osc {
  45. compatible = "fixed-clock";
  46. #clock-cells = <0>;
  47. clock-frequency = <50000000>;
  48. u-boot,dm-pre-reloc;
  49. };
  50. periph_clk: periph-clk {
  51. compatible = "brcm,bcm6345-clk";
  52. reg = <0x10000004 0x4>;
  53. #clock-cells = <1>;
  54. };
  55. timer_clk: timer-clk {
  56. compatible = "brcm,bcm6345-clk";
  57. reg = <0x100000ac 0x4>;
  58. #clock-cells = <1>;
  59. };
  60. };
  61. ubus {
  62. compatible = "simple-bus";
  63. #address-cells = <1>;
  64. #size-cells = <1>;
  65. u-boot,dm-pre-reloc;
  66. pll_cntl: syscon@10000008 {
  67. compatible = "syscon";
  68. reg = <0x10000008 0x4>;
  69. };
  70. syscon-reboot {
  71. compatible = "syscon-reboot";
  72. regmap = <&pll_cntl>;
  73. offset = <0x0>;
  74. mask = <0x1>;
  75. };
  76. periph_rst: reset-controller@10000010 {
  77. compatible = "brcm,bcm6345-reset";
  78. reg = <0x10000010 0x4>;
  79. #reset-cells = <1>;
  80. };
  81. wdt: watchdog@1000009c {
  82. compatible = "brcm,bcm6345-wdt";
  83. reg = <0x1000009c 0xc>;
  84. clocks = <&periph_osc>;
  85. };
  86. wdt-reboot {
  87. compatible = "wdt-reboot";
  88. wdt = <&wdt>;
  89. };
  90. gpio1: gpio-controller@100000c0 {
  91. compatible = "brcm,bcm6345-gpio";
  92. reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
  93. gpio-controller;
  94. #gpio-cells = <2>;
  95. ngpios = <20>;
  96. status = "disabled";
  97. };
  98. gpio0: gpio-controller@100000c4 {
  99. compatible = "brcm,bcm6345-gpio";
  100. reg = <0x100000c4 0x4>, <0x100000cc 0x4>;
  101. gpio-controller;
  102. #gpio-cells = <2>;
  103. status = "disabled";
  104. };
  105. uart0: serial@10000180 {
  106. compatible = "brcm,bcm6345-uart";
  107. reg = <0x10000180 0x18>;
  108. clocks = <&periph_osc>;
  109. status = "disabled";
  110. };
  111. uart1: serial@100001a0 {
  112. compatible = "brcm,bcm6345-uart";
  113. reg = <0x100001a0 0x18>;
  114. clocks = <&periph_osc>;
  115. status = "disabled";
  116. };
  117. periph_pwr: power-controller@1000184c {
  118. compatible = "brcm,bcm6328-power-domain";
  119. reg = <0x1000184c 0x4>;
  120. #power-domain-cells = <1>;
  121. };
  122. lsspi: spi@10000800 {
  123. compatible = "brcm,bcm6358-spi";
  124. reg = <0x10000800 0x70c>;
  125. #address-cells = <1>;
  126. #size-cells = <0>;
  127. clocks = <&periph_clk BCM63268_CLK_SPI>;
  128. resets = <&periph_rst BCM63268_RST_SPI>;
  129. spi-max-frequency = <20000000>;
  130. num-cs = <8>;
  131. status = "disabled";
  132. };
  133. hsspi: spi@10001000 {
  134. compatible = "brcm,bcm6328-hsspi";
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. reg = <0x10001000 0x600>;
  138. clocks = <&periph_clk BCM63268_CLK_HSSPI>, <&hsspi_pll>;
  139. clock-names = "hsspi", "pll";
  140. resets = <&periph_rst BCM63268_RST_SPI>;
  141. spi-max-frequency = <50000000>;
  142. num-cs = <8>;
  143. status = "disabled";
  144. };
  145. leds: led-controller@10001900 {
  146. compatible = "brcm,bcm6328-leds";
  147. reg = <0x10001900 0x24>;
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. status = "disabled";
  151. };
  152. ehci: usb-controller@10002500 {
  153. compatible = "brcm,bcm63268-ehci", "generic-ehci";
  154. reg = <0x10002500 0x100>;
  155. phys = <&usbh>;
  156. big-endian;
  157. status = "disabled";
  158. };
  159. ohci: usb-controller@10002600 {
  160. compatible = "brcm,bcm63268-ohci", "generic-ohci";
  161. reg = <0x10002600 0x100>;
  162. phys = <&usbh>;
  163. big-endian;
  164. status = "disabled";
  165. };
  166. usbh: usb-phy@10002700 {
  167. compatible = "brcm,bcm63268-usbh";
  168. reg = <0x10002700 0x38>;
  169. #phy-cells = <0>;
  170. clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>;
  171. clock-names = "usbh", "usb_ref";
  172. power-domains = <&periph_pwr BCM63268_PWR_USBH>;
  173. resets = <&periph_rst BCM63268_RST_USBH>;
  174. status = "disabled";
  175. };
  176. memory-controller@10003000 {
  177. compatible = "brcm,bcm6328-mc";
  178. reg = <0x10003000 0x894>;
  179. u-boot,dm-pre-reloc;
  180. };
  181. };
  182. };