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u-boot
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arm
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mach-uniphier
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sc64-regs.h

sc64-regs.h 1.2 KB
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  1. /* SPDX-License-Identifier: GPL-2.0+ */
    2. 

  2. /*
    3. 

  3.  * UniPhier SC (System Control) block registers for ARMv8 SoCs
    4. 

  4.  *
    5. 

  5.  * Copyright (C) 2016 Socionext Inc.
    6. 

  6.  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
    7. 

  7.  */
    8. 

  8. 

  9. #ifndef SC64_REGS_H
    10. 

  10. #define SC64_REGS_H
    11. 

  11. 

  12. #define SC_BASE_ADDR		0x61840000
    13. 

  13. 

  14. #define SC_RSTCTRL		(SC_BASE_ADDR | 0x2000)
    15. 

  15. #define SC_RSTCTRL3		(SC_BASE_ADDR | 0x2008)
    16. 

  16. #define SC_RSTCTRL4		(SC_BASE_ADDR | 0x200c)
    17. 

  17. #define SC_RSTCTRL5		(SC_BASE_ADDR | 0x2010)
    18. 

  18. #define SC_RSTCTRL6		(SC_BASE_ADDR | 0x2014)
    19. 

  19. #define SC_RSTCTRL7		(SC_BASE_ADDR | 0x2018)
    20. 

  20. 

  21. #define SC_CLKCTRL		(SC_BASE_ADDR | 0x2100)
    22. 

  22. #define SC_CLKCTRL3		(SC_BASE_ADDR | 0x2108)
    23. 

  23. #define SC_CLKCTRL4		(SC_BASE_ADDR | 0x210c)
    24. 

  24. #define SC_CLKCTRL5		(SC_BASE_ADDR | 0x2110)
    25. 

  25. #define SC_CLKCTRL6		(SC_BASE_ADDR | 0x2114)
    26. 

  26. #define SC_CLKCTRL7		(SC_BASE_ADDR | 0x2118)
    27. 

  27. 

  28. #define SC_CA72_GEARST		(SC_BASE_ADDR | 0x8000)
    29. 

  29. #define SC_CA72_GEARSET		(SC_BASE_ADDR | 0x8004)
    30. 

  30. #define SC_CA72_GEARUPD		(SC_BASE_ADDR | 0x8008)
    31. 

  31. #define SC_CA53_GEARST		(SC_BASE_ADDR | 0x8080)
    32. 

  32. #define SC_CA53_GEARSET		(SC_BASE_ADDR | 0x8084)
    33. 

  33. #define SC_CA53_GEARUPD		(SC_BASE_ADDR | 0x8088)
    34. 

  34. #define   SC_CA_GEARUPD			(1 << 0)
    35. 

  35. 

  36. #endif /* SC64_REGS_H */
    37.