sc64-regs.h 1.2 KB

123456789101112131415161718192021222324252627282930313233343536
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * UniPhier SC (System Control) block registers for ARMv8 SoCs
  4. *
  5. * Copyright (C) 2016 Socionext Inc.
  6. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  7. */
  8. #ifndef SC64_REGS_H
  9. #define SC64_REGS_H
  10. #define SC_BASE_ADDR 0x61840000
  11. #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
  12. #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
  13. #define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
  14. #define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
  15. #define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
  16. #define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
  17. #define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
  18. #define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
  19. #define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
  20. #define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
  21. #define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
  22. #define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
  23. #define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
  24. #define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
  25. #define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
  26. #define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
  27. #define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
  28. #define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
  29. #define SC_CA_GEARUPD (1 << 0)
  30. #endif /* SC64_REGS_H */