sbc.c 2.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011-2015 Panasonic Corporation
  4. * Copyright (C) 2015-2017 Socionext Inc.
  5. * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
  6. */
  7. #include <linux/io.h>
  8. #include "../init.h"
  9. #include "sbc-regs.h"
  10. #define SBCTRL0_ADMULTIPLX_PERI_VALUE 0x33120000
  11. #define SBCTRL1_ADMULTIPLX_PERI_VALUE 0x03005500
  12. #define SBCTRL2_ADMULTIPLX_PERI_VALUE 0x14000020
  13. #define SBCTRL0_ADMULTIPLX_MEM_VALUE 0x33120000
  14. #define SBCTRL1_ADMULTIPLX_MEM_VALUE 0x03005500
  15. #define SBCTRL2_ADMULTIPLX_MEM_VALUE 0x14000010
  16. /* slower but LED works */
  17. #define SBCTRL0_SAVEPIN_PERI_VALUE 0x55450000
  18. #define SBCTRL1_SAVEPIN_PERI_VALUE 0x07168d00
  19. #define SBCTRL2_SAVEPIN_PERI_VALUE 0x34000009
  20. #define SBCTRL4_SAVEPIN_PERI_VALUE 0x02110110
  21. /* faster but LED does not work */
  22. #define SBCTRL0_SAVEPIN_MEM_VALUE 0x55450000
  23. #define SBCTRL1_SAVEPIN_MEM_VALUE 0x06057700
  24. /* NOR flash needs more wait counts than SRAM */
  25. #define SBCTRL2_SAVEPIN_MEM_VALUE 0x34000009
  26. #define SBCTRL4_SAVEPIN_MEM_VALUE 0x02110210
  27. static void __uniphier_sbc_init(int savepin)
  28. {
  29. /*
  30. * Only CS1 is connected to support card.
  31. * BKSZ[1:0] should be set to "01".
  32. */
  33. if (savepin) {
  34. writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
  35. writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
  36. writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
  37. writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
  38. } else {
  39. writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
  40. writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
  41. writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
  42. }
  43. if (boot_is_swapped()) {
  44. /*
  45. * Boot Swap On: boot from external NOR/SRAM
  46. * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
  47. *
  48. * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
  49. * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
  50. */
  51. writel(0x0000bc01, SBBASE0);
  52. } else {
  53. /*
  54. * Boot Swap Off: boot from mask ROM
  55. * 0x40000000-0x41ffffff: mask ROM
  56. * 0x42000000-0x43efffff: memory bank (31MB)
  57. * 0x43f00000-0x43ffffff: peripherals (1MB)
  58. */
  59. writel(0x0000be01, SBBASE0); /* dummy */
  60. writel(0x0200be01, SBBASE1);
  61. }
  62. }
  63. void uniphier_sbc_init_admulti(void)
  64. {
  65. __uniphier_sbc_init(0);
  66. }
  67. void uniphier_sbc_init_savepin(void)
  68. {
  69. __uniphier_sbc_init(1);
  70. }